CN116266472A - Memory device cross matrix parity check - Google Patents

Abstract

The present disclosure describes methods, devices, and systems related to cross matrix parity check in memory devices. In an example, a first plurality of parity data sets, each protecting data stored in a row of memory cells of an array, to memory cells in the array may be written to the array. Further, a second plurality of sets of parity data, each protecting data stored in a column of memory cells of the array, to memory cells in the array may be written to the array. The first plurality of parity data sets and the second plurality of parity data sets may be sent to a processor for further ECC processing. Error correction data indicating a cluster of data containing a threshold number of errors may be received from a processor. Error correction may be performed on the data clusters.

Description

Memory device cross matrix parity check

technical field

The present disclosure generally relates to memory device interleaving matrix parity checking.

Background technique

Memory devices are often provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes Random Access Memory (RAM), DRAM and Synchronous Dynamic Random Access Memory (SDRAM), among others. Non-volatile memory provides permanent data by retaining stored data when power is not supplied and can include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM) , Erasable Programmable ROM (EPROM) and resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM) and magnetoresistive random access memory (MRAM) and other memories .

Memory is also used as volatile and non-volatile data storage devices in a wide range of electronic applications. For example, non-volatile memory can be used in personal computers, portable memory sticks, digital cameras, cellular telephones, portable music players such as MP3 players, movie players, and other electronic devices. Memory cells can be arranged in arrays, where the arrays are used in a memory device.

The memory may be part of a memory module, such as a dual inline memory module (DIMM), used in a computing device. For example, a memory module may include volatile memory, such as DRAM, and/or non-volatile memory, such as Flash memory or RRAM, for example. DIMMs can be used as main memory in computing systems.

Contents of the invention

Aspects of the present disclosure are directed to a memory device using interleaved matrix parity, comprising: an array (130, 219) of memory cells; control circuitry (140) coupled to the array, wherein the control circuitry The system is configured to: write a first plurality of parity data sets to memory cells in the array (203), the first plurality of parity data sets each protecting memory stored in the array data in a row of cells; writing a second plurality of parity data sets to memory cells in the array, each of the second plurality of parity data sets protecting a memory cell stored in the array data in a meta column; sending the first plurality of parity sets and the second plurality of parity sets to a processor; based on the first plurality of parity sets and the second plurality receiving error correction data from the processor, wherein the error correction data is indicative of a data cluster containing a threshold number of errors; and performing an error correction operation on the data cluster.

Another aspect of the present disclosure is directed to a method of using a memory device for interleaved matrix parity, comprising: writing: a first set of parity data to an access line of a memory cell coupled to an array ( 204) to protect data in a second portion of the memory cell coupled to the access line; and a second set of parity data written to the sensing of the memory cell coupled to the array A first portion of a line (205) to protect data of a memory cell coupled into a second portion of the sense line, wherein the second parity data set is received from a processor; the first parity sending a set of parity data and the second set of parity data to the processor; receiving for memory of the array based on the first set of parity data and the second set of parity data an instruction to perform an error correction operation on a cluster of data in a cell; and perform the error correction operation on the cluster of data.

Yet another aspect of the present disclosure is directed to a system using crossbar parity, comprising: a processor (102); and a memory device (120), coupled to the processor, the memory device comprising: a memory an array of cells (130, 219); and control circuitry coupled to the array, wherein the control circuitry is configured to: write: a first plurality of parity data sets to respective ones of the memory cells a first portion coupled to a corresponding access line (204) of the array to protect data in a corresponding second portion of the memory cells coupled to its corresponding access line; and a second plurality of parity data sets written to second portions of the memory cells each coupled to respective sense lines (205) of the array to protect data in respective second portions of the memory cells coupled to their respective sense lines; parity data sets and the second plurality of parity data sets are sent to the processor; wherein the processor is configured to: receive the first plurality of parity data sets and the second plurality of parity data sets two or more sets of parity data; and generating an instruction to perform an error correction operation on a data cluster stored in a portion of a memory cell coupled to one of the access lines; and sent to the memory device.

Description of drawings

1 is a block diagram of an apparatus in the form of a computing system including a memory system, according to various embodiments of the present disclosure.

Figure 2A illustrates a schematic diagram of a portion of a memory array according to various embodiments of the disclosure.

2B illustrates a schematic diagram of a portion of a memory array for interleaved matrix parity checking, according to various embodiments of the present disclosure.

2C illustrates a schematic diagram of a portion of a memory array for interleaved matrix parity, according to various embodiments of the disclosure.

FIG. 3 is a flowchart of a method for cross matrix parity checking in a memory device according to various embodiments of the present disclosure.

Detailed ways

The present disclosure relates to the described methods, devices and systems related to memory device interleaved matrix parity checking. In an example, a first plurality of parity data sets to memory cells in an array that each protect data stored in a row of memory cells of the array can be written to the array. Additionally, a second plurality of parity data sets to memory cells in the array each protecting data stored in a column of memory cells of the array may be written to the array. The first plurality of parity data sets and the second plurality of parity data sets may be sent to a processor or host for further ECC processing. Error correction data can be received from a processor or host indicating a cluster of data containing a threshold number of errors. Error correction may be performed on the data clusters.

The memory device may be a non-volatile memory device. One example of a non-volatile memory device is a "NAND" (NAND) memory device (also known as flash memory technology). Other examples of non-volatile memory devices are described below in conjunction with FIG. 1 . Non-volatile memory devices are packages of one or more die. Each die may consist of one or more planes. Planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (eg, NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page is made up of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. A block refers hereinafter to the cells of a memory device used to store data, and may include a group of memory cells, a group of word lines, a word line, or individual memory cells. For some memory devices, a block (hereinafter also referred to as a "memory block") is the smallest area that can be erased. Pages cannot be erased individually, only entire blocks.

Each of the memory devices may include one or more arrays of memory cells. Depending on the cell type, a cell can store one or more bits of binary information and have various logic states related to the number of bits stored. Logical states may be represented by binary values, such as "0" and "1," or combinations of such values. There are various types of cells such as single-level cells (SLC), multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC). For example, an SLC can store one bit of information and have two logic states.

Some NAND memory devices employ a floating gate architecture in which memory access is controlled based on relative voltage changes between bit lines and word lines. Other examples of NAND memory devices may employ alternative gate architectures, which may include the use of a word line layout that may allow charge corresponding to a data value to be trapped within the memory cell based on the properties of the material used to construct the word line.

When a memory device is accessed a high number of times, memory cells storing data may experience failure due to these repeated accesses to a particular row of memory cells (eg, cells coupled to an access line). These intermittent failures caused by data errors can affect the reading of data and can disable damaged memory by repairing data, reading and writing data additional times, and altering the timing and/or voltage associated with memory cells cells and so on to reduce. The number of errors in a memory cell row can be determined by using parity data that protects the memory cell row (e.g., horizontal parity data associated with an access line) and the memory cell row Both columns (eg, vertical parity data associated with sense lines). By doing so, the memory cell rows that encountered errors, or data stored in those memory cell rows containing errors, can be located within the memory device because the interleaved matrix parity data can help pinpoint errors stored in memory cells more targeted position.

Additionally, the interleaved matrix parity data can be used to locate specific clusters of data that are part of a row for error correction, thereby avoiding the need for error correction on an entire row of memory cells. Furthermore, weak rows, or rows with a certain error threshold, can be disabled or passed on for writing in order to improve the performance of the memory device. An additional layer of error correction fine-tuning is achieved by identifying and tracking the vertical parity of the data in the memory cells. Analysis of the horizontal and vertical parity data can be performed by the host, allowing various memory devices to be used with cross-matrix parity settings without altering or changing the memory device other than some setting and/or software changes. In addition, performing error correction on the data reduces the bit error rate (BER) and increases the reliability of the data.

By performing these methods on memory cells storing data with a threshold number (or number) of errors, the number of errors in the data stored in the memory cells can be maintained below a level at which the memory cannot be corrected anymore. For example, an error correction method and/or system may be limited in the number of correctable data bits and/or portions that the method or system can correct. Once a memory array or a single row of cells exceeds these limits, the memory array can become uncorrectable. The memory array remains correctable by maintaining the error rate below a threshold.

ECC operations may include generating parity data, for example, by performing XOR and/or RAID operations on data stored in memory cells of the array. Parity data may be stored (eg, written to) in volatile and/or non-volatile memory devices. In some examples, parity data may be embedded in data in volatile memory devices and/or non-volatile memory devices.

Data stored in volatile and/or non-volatile memory devices can be reconstructed using parity data. The host and/or the memory device's controller can receive (eg, read) parity data from the memory device and reconstruct the data in response to a read failure. Read failures may be due to memory corruption in the memory device.

In the following Detailed Description of the Disclosure, reference is made to the accompanying drawings which form a part hereof, and which show by way of illustration how various embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the disclosed embodiments, and it is to be understood that other embodiments may be utilized and that procedural, electrical, and/or or structural changes. As used herein, the designators "M," "N," "X," and "Y" indicate that the particular features so designated may be included with various embodiments of the present disclosure.

As used herein, a "plurality" of something may refer to one or more of such things. For example, a plurality of memory cells may refer to one or more memory cells. Additionally, as used herein, designators such as "M," "P," and "J," especially with respect to reference numerals in the drawings, indicate that the particular features so designated are compatible with various embodiments of the present disclosure. included together.

The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number of the drawing and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar numerals. As will be appreciated, elements shown in the various embodiments herein may be added, exchanged, and/or eliminated in order to provide additional embodiments of the present disclosure. Additionally, the proportions and relative scales of elements provided in the figures are intended to illustrate various embodiments of the present disclosure and are not intended to be limiting.

1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 120 according to various embodiments of the present disclosure. As used herein, memory device 120, memory array 130, and/or logic 140 (eg, control logic), and/or read/latch circuitry 150 may also be individually considered a "device."

System 100 includes a memory controller 102 coupled (eg, connected) to a memory device 120 that includes a memory array 130 . Examples of memory device 120 include NAND devices. In various embodiments, the NAND device includes ECC capability performed by the error correction code (ECC) component 115 of the memory device 120 . ECC component 115 may include error correction circuitry and/or components to perform multiple error corrections. An ECC engine (not illustrated) may be coupled to memory array 130 that corrects errors when data is read from memory array 130 through output buffers.

Memory controller 102 may be coupled to host 102 . Host 102 may be a host system such as a personal laptop computer, desktop computer, digital camera, smart phone, or memory card reader, among various other types of hosts. Host 102 may include a host controller external to memory device 120. Host controller 113 may include control circuitry, eg, hardware, firmware, and/or software. In one or more embodiments, host 102 may include a processor, which is a Complex Instruction Set Computer (CISC) type processor. In one or more embodiments, host controller 113 may be an application specific integrated circuit (ASIC) coupled to a printed circuit board that includes the physical interface. Host 102 may include a system motherboard and/or backplane, and may include multiple processing resources (eg, one or more processors, microprocessors, or some other type of control circuitry).

The host 102 may include an ECC component 117 for performing ECC operations and/or processing parity data to determine locations or cells storing data containing errors. ECC component 117 can receive parity data used to protect both vertical and horizontal data and use this interleaved matrix parity method to more efficiently manage errors in memory array 130 of memory device 120 .

For clarity, system 100 has been simplified to focus on features of particular relevance to the present disclosure. For example, memory array 130 may be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array. Array 130 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines. Although a single array 130 is shown in FIG. 1 , embodiments are not limited thereto. For example, memory device 120 may include multiple arrays 130 (eg, multiple rows or pages of NAND cells). Memory array 130 may include a row parity portion 145 toward the end of the row to store row parity data, as will be further described below in connection with FIGS. 2A-2B . Additionally, memory array 130 may include a column parity portion 147 toward the bottom of a column (as illustrated) of the array to store column parity data, as will be described further below.

Memory device 120 may include control logic 140, eg, hardware, firmware, and/or software. In one or more embodiments, control logic 140 may be an application specific integrated circuit (ASIC) coupled to a printed circuit board that includes the physical interface. In some embodiments, control logic 140 may be a media controller such as a DRAM memory controller or a non-volatile memory express (NVMe) controller. For example, control logic 140 may be configured to perform operations on memory device 130 such as copying, writing, reading, error correction, and the like. Additionally, controller 123 may include dedicated circuitry and/or instructions to perform the various operations described herein. That is, in some embodiments, control logic 140 may include circuitry and/or instructions executable to store addresses (or locations) of a row of memory cells that contain a particular number (or numbers) of errors. In some embodiments, error correction code (ECC) circuitry 115 and/or instructions provided to control logic 140 may control performing repair operations on rows of memory cells that have a certain number of errors.

Memory array 130 may include additional row or row portions or registers (eg, "column parity" 147 or "row parity" 145) for storing parity data for a particular row or column of memory cells. A particular row of memory cells can be associated with parity data corresponding to the row of memory cells. As an example, an ECC operation may be performed and a parity value may be indicated to protect the row of cells. The parity data can be sent to the host 102 and in response to a message from the host to perform a repair operation based on the parity data, the address of that particular row can be accessed and the memory in the row at that address can be repaired data in the cell. Additionally, the specific address of the row to be repaired can be added to the list used to perform the repair operation.

Memory device 120 includes address circuitry 142 to latch address signals provided over bus 154 (eg, a data bus) through I/O circuitry 144 . Address signals may also be sent by memory controller 102 and received by control logic 140 (eg, via address circuitry 142 and/or via bus 154). Address signals are received and decoded by row decoder 146 and column decoder 152 to access memory array 130 . Data may be read from memory array 130 by sensing voltage and/or current changes on the data lines using read/latch circuitry 150 . Read/latch circuitry 150 can read and latch pages (eg, rows) of data from memory array 130 . I/O circuitry 144 may be used for bi-directional data communication with host 110 via bus 154 . Write circuitry 148 is used to write data to memory array 130 . Control logic 140 includes non-volatile memory (“NVM”) 149 that may be used to store data from volatile memory in the event of a power outage or power cycle of memory device 120 . While the example illustrates non-volatile memory 149 within control logic 140, the example is not limited thereto. Non-volatile memory 149 may be located at other addresses within memory device 120 . In another such example, non-volatile memory 149 may be stored in portions of memory array 130 .

In some embodiments, control logic 140 decodes signals provided by memory controller 102 over bus 154 . Although bus 154 is illustrated as a single bus for sending address signals, bi-directional communications, decoding signals, etc., embodiments are not so limited. For example, bus 154 may be divided into more than one bus, where each bus is designated for a particular signal (eg, a bus for address signals and/or commands, a bus for bi-directional communication, etc.). These signals may include chip enable signals, write enable signals, and address latch signals for controlling operations performed on memory array 130 , including data read, data write, and data erase operations. In various embodiments, logic 140 is responsible for executing instructions from host 110 . Logic 140 may be a state machine, a sequencer, or some other type of control circuitry. Logic 140 may be implemented in hardware, firmware, and/or software. Although logic 140 is illustrated as being coupled to particular components (eg, to memory array 130 and address circuitry 142 ), a controller may be coupled to any of the components within memory device 120 .

FIG. 2A illustrates a schematic diagram of a portion of a memory array 219 according to various embodiments of the disclosure. Array 219 includes memory cells (generally referred to as memory cells 203, and more specifically 203-0 through 203-J) coupled to rows of access lines 204-0, 204-1 , 204-2, 204-3, 204-4, 204-5, 204-6, . 205-2, 205-3, 205-4, 205-5, 205-6, 205-7, . . . , 205-D (commonly referred to as sensing lines 205). Each row of cells coupled to an access line is illustrated as ROW 0 221-0 through ROW P 221-P to indicate the first row of cells along access line 204-0. Furthermore, memory array 219 is not limited to a particular number of access and/or sense lines, and the use of the terms "row" and "column" does not imply a particular physical structure and/or orientation. Although not shown, in some examples, each column of memory cells can be associated with a corresponding pair of complementary sense lines.

Each column of memory cells (eg, columns 223-0 through 223-11) can be coupled to sense circuitry, such as a sense amplifier. In this example, the sensing circuitry may include sensors coupled to respective sense lines 205-0, 205-1, 205-2, 205-3, 205-4, 205-5, 205-6, 205-7, . . . , Multiple sense amplifiers (not illustrated) of 205-D. Sense amplifiers may be coupled to input/output (I/O) lines (eg, local I/O lines, not shown) via access devices (eg, transistors, not shown).

As will be described further below in connection with FIG. 2B, memory cell rows "ROW P-3" 221-8, "ROW P-2" coupled to access lines 204-8, 204-9, 204-10, and 204-P 221-9, "ROW P-1" 221-10, and "ROW P" 221-P may be used to store a plurality of parity data that protects the vertical data stored in the memory array 219. For example, data stored in memory cells coupled to sense line 205-0 and access lines 204-0 through 204-7 (eg, the first byte stored in first cell column 223-0) can be vertically protected by parity data stored in memory cells coupled to sense line 205-0 and to access lines 204-8 through 204-P (e.g., four vertically stored parity bits can be protects 8 vertically stored data bits). Although 8 bits of data and 4 bits of parity are described in this example, other examples are not limited thereto. The number of data bits may exceed 8 bits, as indicated by the dot between ROW 7 221-7 and ROWP-3 221-8.

Likewise, row parity bits may be stored in memory cells coupled to access lines 204-0 through 204-7 (in ROW 0 221-0 through ROW 7 221-7), and to sense lines 205-A, 205-B, 205-C, 205-D. In this way, data stored along the cell level coupled to a particular access line 204 may be protected. For example, data stored in memory cells coupled to access line 204-0 and coupled to sense lines 205-0 through 205-7 may be stored in memory cells coupled to access line 204-0 and coupled to sense lines 205-0 through 205-7. Protection of parity data in memory cells of 205-A, 205-B, 205-C, and 205-D (e.g., 4 horizontally stored parity bits stored at the end of a row of cells will protect memory 8 horizontally stored data bits in the same cell row). In this way, the vertical parity bit and the horizontal parity bit together can provide additional ECC protection. As an example, the data bits stored in cell 203-0 may be protected by two vertical parity bits and a horizontal parity bit.

In some embodiments, row parity can be determined by the memory device and column parity can be determined by the host. In this way, memory devices that lack the hardware capability to monitor vertical data parity can still be used with the interleaved matrix parity method described herein. In some embodiments, the memory device may determine both row parity data and column parity data and send both parity data to the host for processing and/or determining where the error is located in a memory cell of the array Location.

Figure 2B illustrates a schematic diagram of a portion of the memory array 219-2 for interleaved matrix parity checking, according to various embodiments of the present disclosure. 2B is a further illustration of FIG. 2A illustrating ROW 0 221-0 through P 221-P and "COL0" 223-0 through "COL 11" 223-11, with individual memory cells not shown for ease of reference and explanation. Each row of cells 221-0 to 221-7 stores data (horizontal description), such as "DATA 0" 227-0 to "DATA 7" 227-7. Each data set stored horizontally is protected by row parity data. For example, "DATA 0" 227-0 is protected by the "R0 Parity" 231-0 level stored in cells of "ROW 0" 221-0 and COLUMN "8" 223-8 through "11" 223-11. Each of the DATA 0 225-0 to DATA 7 225-7 rows is protected by a corresponding row parity data R0 231-0 to R7 231-7.

Likewise, each cell 223-0 through 223-7 stores data (vertically illustrated), such as data 225-0 in "COL 0" 223-0 through data 225-7 in "COL 7" 223-7 . Each data set stored vertically is protected by vertical parity data. For example, the data 225-0 in "COL 0" 223-0 is vertically protected by Column 0Group Parity ("C0 GP") 229-0, stored in "COL 0" 223-0 and ROW "P-3" 221-8 into the cell of "P" 221-P. Likewise, vertical data is protected by each of C0 GP 229-0 to C7 GP 229-7, respectively.

Cross matrix parity is provided using sets of horizontal parity data (R0 Parity 231-0 to R7 Parity 231-7) along with sets of vertical parity data (C0 GP 229-0 to C7 GP 229-7) to More closely pinpoint the location of errors in memory cells. Additionally, a single horizontal parity value may not provide sufficient parity protection to recover data when a threshold number of bit errors is reached or exceeded. By adding in the vertical parity value, additional errors that would otherwise prevent the cell's data from being recovered can be corrected.

While processing interleaved matrix parity values in a memory device (eg, memory device 120 in FIG. 1 ) can be beneficial, processing interleaved matrix parity values can be prevented interchangeably using different memory devices without changing Memory device controllers and other internal hardware and/or firmware elements. By offloading the determination of column parity data and/or cross matrix parity values to the host, multiple different memory devices can be used without changing memory controllers and other elements. For example, changing the memory device may use newer software or firmware, but the host may provide the functionality of the interleaved matrix parity.

Figure 2C illustrates a schematic diagram of a portion of the memory array 219-3 for interleaved matrix parity checking according to various embodiments of the present disclosure. Figure 2C is a further illustration of Figures 2A-2B. Furthermore, similar to FIG. 2B , illustrating ROW0 221 -0 through P 221 -P and "COL 0 " 223 - 0 through " COL 11 " 223 - 11 , individual memory cells are not shown for ease of reference and explanation. Each row of cells 221-0 to 221-7 stores data (horizontal description), such as "DATA0" 227-0 to "DATA 7" 227-7. Each data set stored horizontally is protected by row parity data. For example, "DATA 0" 227-0 is protected by the "ROParity" 231-0 level stored in cells of "ROW 0" 221-0 and COLUMN "8" 223-8 through "11" 223-11. Each of the DATA 0 225-0 through DATA 7 225-7 rows is protected by a corresponding row parity data R0 231-0 through R7 231-7.

As illustrated in Figure 2C, particular memory cell locations are indicated as having corrupt data (labeled "D" in Figure 2C) or being in a weak (labeled "W" in Figure 2C) row of cells. As an example, memory cells in ROW 4 221-4 and COL 2223-2 and COL3 223-3 are indicated as bad cells. Additionally, memory cells in ROW 2 221-2 and COL 6 223-6 and COL 7 223-7 are indicated as bad cells. Additionally, the memory cell of ROW 5 221-5 is indicated as being in a weak ("W") cell row. Row parity data R2 Parity 231-2 will reflect the damaged cells of that row in COL 6 and 7, and column parity data C6 GP 229-6 and C7 GP 229-7 for vertical parity. Likewise, the row parity data R4 Parity 231-4 will reflect the damaged cells of the corresponding rows in COL 2 and 3, and the column parity data C2 GP 229-2 and C3 GP 229-3.

In this way, interleaved matrix parity by combining row and column parity data can be used to determine a more specific location in a memory cell for performing error correction. In one example, error correction can be performed on a particular cluster of data, as in the two memory cells mentioned above. In one example, a particular row may be indicated for error correction when an entire row has an error value above a threshold, indicating that the row of cells is a weak row in terms of data. Weak rows can be disabled and no longer used, or further attempts to correct the data in the row can be performed if the required error correction strength is available for error correction. Types of error correction for clustering methods may include Reed Solomon error correction operations, among many others.

FIG. 3 is a flowchart of a method 351 for cross matrix parity checking in a memory device according to an embodiment of the disclosure. In this example, the memory device is a NAND device. Method 351 may be performed by processing logic that may comprise hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., on a processing device instructions to run or execute), or a combination thereof. In some embodiments, the method 351 is performed by the control logic 140 in FIG. 1 in conjunction with the ECC component 115 in the memory device 120 and the ECC component 117 of the host. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and illustrated processes may be performed in a different order, and some processes may be performed in parallel. Additionally, one or more procedures may be omitted in various embodiments. Therefore, not all procedures are required in every embodiment. Other process flows are possible.

At block 353, the method 351 may include writing the first set of parity data to a first portion of the memory cell coupled to an access line of the array to protect a second portion of the memory cell coupled to the access line The data. The first portion of memory cells may be located in a memory array, such as memory array 130 in FIG. 1 . As an example, a first portion of a memory cell coupled to an access line may be adjacent to and before a second portion of the memory cell coupled to an access line, thereby storing adjacent to protected parity data to be horizontally protected ( data as illustrated in Figures 2A to 2C).

At block 355, the method 351 may include writing a second set of parity data to a first portion of the memory cell coupled to the sense line of the array to protect a second portion of the memory cell coupled to the sense line The data. As an example, a first portion of a memory cell coupled to a sense line may be adjacent to and prior to a second portion of the memory cell, thereby storing adjacent to protected parity data to be vertically protected (as in FIGS. 2A-2C ). data as described in ).

At block 357, the method 351 may include sending the first set of parity data and the second set of parity data to the host. The host can perform analysis on the first set of parity data and the second set of parity data to determine which data in which memory cells to perform error correction on. The host can use the first set of parity data to determine which memory cell coupled to which particular access line is storing data to be error corrected. The host can use the second set of parity data to determine which memory cell coupled to which particular sense line is storing data to be error corrected.

Based on the parity data corresponding to each of the access lines, the number of errors associated with data in the first portion of the memory cells may exceed a threshold number of errors. It may be determined that data for a first portion of the memory cells coupled to the access line exceeds a threshold number. Based on the parity data corresponding to each of the sense lines, the number of errors associated with the data of the first portion of the memory cells coupled to the sense lines may exceed a threshold number of errors. It may be determined that the first portion exceeds a threshold number. The number of errors in memory cells of a particular cell row can be determined by using both the first set of parity data and the second set of parity data.

At block 359, the method 351 may include receiving instructions to perform error correction operations on clusters of data in memory cells of the array based on the first set of parity data and the second set of parity data. Instructions can be received by the memory device and sent by the host. Error correction operations can be performed on memory cells corresponding to at least one of the stored row addresses. Error correcting operations may involve correcting a certain number of errors. In some examples, the error correction operation may include altering the voltage of the cell associated with the address or altering the access time of the cell associated with the address.

At block 361, the method may include performing error correction operations on the data clusters. Error correction operations may be performed by the ECC component of the memory device. For example, the host may send instructions indicating which clusters of data or rows of memory cells are to be corrected and/or disabled (eg, no longer used). In response, the memory device may correct or disable the data stored in the indicated row of memory cells.

Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that arrangements aimed at achieving the same results may be substituted for the specific embodiments shown. It is intended that the present invention cover adaptations or variations of various embodiments of the present disclosure. It should be understood that the foregoing description has been made in an illustrative manner and not in a limiting manner. Combinations of the above-described embodiments, and other embodiments not specifically described herein, will be readily apparent to those of skill in the art upon reviewing the above description. The scope of the various embodiments of the present disclosure includes other applications in which the structures and methods described above are used. Therefore, the scope of various embodiments of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

In the foregoing Detailed Description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments of the disclosure have to use more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims (18)

1. A memory device using cross matrix parity checking, comprising:

an array of memory cells (130, 219);

control circuitry (140) coupled to the array, wherein the control circuitry is configured to:

writing a first plurality of parity data sets to memory cells (203) in the array, the first plurality of parity data sets each protecting data stored in a row of memory cells of the array;

writing a second plurality of parity data sets to memory cells in the array, the second plurality of parity data sets each protecting data stored in a column of memory cells of the array;

sending the first plurality of parity sets and the second plurality of parity sets to a processor;

receiving error correction material from the processor based on the first plurality of parity sets and the second plurality of parity sets, wherein the error correction data is indicative of a data cluster including a threshold number of errors; and

Performing an error correction operation on the data cluster.

2. The memory device of claim 1, wherein the control circuitry is configured to perform the error correction operation using a reed-solomon error correction operation.

3. The memory device of claim 1, wherein the data clusters are portions of data stored in rows of memory cells coupled to access lines (204).

4. The memory device of claim 1, wherein the data cluster is a row of memory cells coupled to an access line (204).

5. The memory device of claim 1, wherein the first plurality of parity data sets is used to determine that a row of memory cells of the array includes a plurality of errors exceeding a threshold number of errors.

6. The memory device of any one of claims 1-5, wherein the second plurality of parity data sets is used to determine whether a row of memory cells of the array includes a plurality of errors exceeding a threshold number of errors.

7. The memory device of any one of claims 1-5, wherein the control circuitry is further configured to:

determining the first plurality of parity data sets; and

The second plurality of parity data sets is received from a processor (102).

8. The memory device of any one of claims 1-5, wherein the control circuitry is further configured to determine the first plurality of parity data sets and the second plurality of parity data sets.

9. The memory device of any one of claims 1-5, wherein the control circuitry is configured to perform the repair operation independent of receiving data from an ECC component (115) within the memory indicating which data is to be repaired.

10. A method of using a memory device for cross matrix parity checking, comprising:

will:

a first set of parity data is written to a first portion of memory cells coupled to an access line (204) of the array to protect data in a second portion of memory cells coupled to the access line; and

A second set of parity data is written to a first portion of the memory cells coupled to sense lines (205) of the array to protect data in a second portion of the memory cells coupled to the sense lines, wherein the second set of parity data is received from the processor;

sending the first parity data set and the second parity data set to the processor;

receiving instructions to perform an error correction operation on a data cluster in a memory cell of the array based on the first parity data set and the second parity data set; and

And performing the error correction operation on the data cluster.

11. The method as recited in claim 10, further comprising:

performing an analysis on the first parity data set and the second parity data set to determine which data clusters to perform the error correction operation on; and

Cross matrix parity data is determined using the first parity data set and the second parity data set to determine the location of the data clusters in the array.

12. The method of any of claims 10-11, further comprising determining, based on the first set of parity data corresponding to each of the access lines, that a number of errors associated with the data in the first portion of memory cells exceeds a threshold number of errors.

13. The method of any of claims 10-11, further comprising determining, based on the second set of parity data corresponding to each of the access lines, that a number of errors associated with the data in the second portion of memory cells exceeds a threshold number of errors.

14. The method of any of claims 10-11, further comprising performing the error correction operation in response to receiving the instruction from a host (102).

15. A system for using cross matrix parity check, comprising:

a processor (102); and

A memory device (120) coupled to the processor, the memory device comprising:

an array of memory cells (130, 219); and

Control circuitry coupled to the array, wherein the control circuitry is configured to:

will:

a first plurality of parity data sets is written to a first portion of memory cells each coupled to a respective access line (204) of the array to protect data in a respective second portion of the memory cells coupled to their respective access lines; and

A second plurality of parity data sets is written to a second portion of the memory cells each coupled to a respective sense line (205) of the array to protect data in the respective second portion of the memory cells coupled to their respective sense line; and

Sending the first plurality of parity data sets and the second plurality of parity data sets to the processor;

wherein the processor is configured to:

receiving the first plurality of parity data sets and the second plurality of parity data sets; and

Generating instructions to perform an error correction operation on a data cluster stored in a portion of a memory cell coupled to an access line of the access lines; and

The instructions are sent to the memory device.

16. The system of claim 15, wherein the processor is further configured to locate the data cluster by combining results from the first parity data set and the second parity data set.

17. The system of claim 16, wherein the processor is further configured to generate and send the second plurality of parity sets to the memory device.

18. The system of claim 15, wherein the processor is further configured to send a message to the memory device to disable the damaged row of memory cells.

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