FR3063387B1 - ELECTRONIC COMPONENT EQUIPPED WITH A TRANSISTOR AND PROHIBITED FINGERS TO FORM AT LEAST PART OF A CAPACITIVE COMPONENT WITHIN THE ELECTRONIC COMPONENT - Google Patents
ELECTRONIC COMPONENT EQUIPPED WITH A TRANSISTOR AND PROHIBITED FINGERS TO FORM AT LEAST PART OF A CAPACITIVE COMPONENT WITHIN THE ELECTRONIC COMPONENT Download PDFInfo
- Publication number
- FR3063387B1 FR3063387B1 FR1751499A FR1751499A FR3063387B1 FR 3063387 B1 FR3063387 B1 FR 3063387B1 FR 1751499 A FR1751499 A FR 1751499A FR 1751499 A FR1751499 A FR 1751499A FR 3063387 B1 FR3063387 B1 FR 3063387B1
- Authority
- FR
- France
- Prior art keywords
- electronic component
- fingers
- electrical connection
- transistor
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
- H01L23/5223—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/212—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Junction Field-Effect Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Le composant électronique (1) comprend une partie (2) intégrant un transistor (3) muni d'une électrode de commande (31) et de première et deuxième électrodes (32, 33). Le composant électronique (1) comporte des première, deuxième et troisième bornes de connexion électrique (4, 5, 6) s'étendant sur une face de connexion (7) de ladite partie (2) intégrant le transistor (3), la première borne de connexion électrique (4) étant en lien électrique avec la première électrode (32), la deuxième borne de connexion électrique (5) étant en lien électrique avec la deuxième électrode (33) et la troisième borne de connexion électrique (6) étant en lien électrique avec l'électrode de commande (31). Le composant électronique (1) comporte un premier ensemble (8) de doigts électriquement conducteurs et un deuxième ensemble (9) de doigts électriquement conducteurs, les doigts (8a, 9a) des premier et deuxième ensembles (8, 9) de doigts étant interdigités, au niveau de la face de connexion (7), pour former au moins une partie d'un composant capacitif. Les doigts (8a) du premier ensemble (8) de doigts sont reliés électriquement à la première borne de connexion électrique (4).The electronic component (1) comprises a part (2) integrating a transistor (3) provided with a control electrode (31) and with first and second electrodes (32, 33). The electronic component (1) comprises first, second and third electrical connection terminals (4, 5, 6) extending on a connection face (7) of said part (2) integrating the transistor (3), the first electrical connection terminal (4) being in electrical connection with the first electrode (32), the second electrical connection terminal (5) being in electrical connection with the second electrode (33) and the third electrical connection terminal (6) being in electrical connection with the control electrode (31). The electronic component (1) comprises a first set (8) of electrically conductive fingers and a second set (9) of electrically conductive fingers, the fingers (8a, 9a) of the first and second sets (8, 9) of fingers being interdigitated , at the connection face (7), to form at least part of a capacitive component. The fingers (8a) of the first set (8) of fingers are electrically connected to the first electrical connection terminal (4).
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1751499A FR3063387B1 (en) | 2017-02-24 | 2017-02-24 | ELECTRONIC COMPONENT EQUIPPED WITH A TRANSISTOR AND PROHIBITED FINGERS TO FORM AT LEAST PART OF A CAPACITIVE COMPONENT WITHIN THE ELECTRONIC COMPONENT |
US16/488,003 US10957639B2 (en) | 2017-02-24 | 2018-02-22 | Electronic component having a transistor and interdigitated fingers to form at least a portion of a capacitive component within the electronic component |
PCT/FR2018/050418 WO2018154242A2 (en) | 2017-02-24 | 2018-02-22 | Electronic component having a transistor and interdigitated fingers to form at least a portion of a capacitive component within the electronic component |
EP18709686.2A EP3586360B1 (en) | 2017-02-24 | 2018-02-22 | Electronic component having a transistor and interdigitated fingers to form at least a portion of a capacitive component within the electronic component |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1751499 | 2017-02-24 | ||
FR1751499A FR3063387B1 (en) | 2017-02-24 | 2017-02-24 | ELECTRONIC COMPONENT EQUIPPED WITH A TRANSISTOR AND PROHIBITED FINGERS TO FORM AT LEAST PART OF A CAPACITIVE COMPONENT WITHIN THE ELECTRONIC COMPONENT |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3063387A1 FR3063387A1 (en) | 2018-08-31 |
FR3063387B1 true FR3063387B1 (en) | 2021-05-21 |
Family
ID=59649775
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1751499A Expired - Fee Related FR3063387B1 (en) | 2017-02-24 | 2017-02-24 | ELECTRONIC COMPONENT EQUIPPED WITH A TRANSISTOR AND PROHIBITED FINGERS TO FORM AT LEAST PART OF A CAPACITIVE COMPONENT WITHIN THE ELECTRONIC COMPONENT |
Country Status (4)
Country | Link |
---|---|
US (1) | US10957639B2 (en) |
EP (1) | EP3586360B1 (en) |
FR (1) | FR3063387B1 (en) |
WO (1) | WO2018154242A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP4333304A3 (en) * | 2019-10-31 | 2024-06-05 | Infineon Technologies Austria AG | Semiconductor device and inverter |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW373320B (en) | 1996-05-27 | 1999-11-01 | United Microelectronics Corporaiton | Structure and production method of capacitor of dynamic RAM |
US6410955B1 (en) | 2001-04-19 | 2002-06-25 | Micron Technology, Inc. | Comb-shaped capacitor for use in integrated circuits |
JP3863391B2 (en) | 2001-06-13 | 2006-12-27 | Necエレクトロニクス株式会社 | Semiconductor device |
JP4024572B2 (en) * | 2002-03-28 | 2007-12-19 | ユーディナデバイス株式会社 | Device with interdigital capacitor |
US7022581B2 (en) | 2004-07-08 | 2006-04-04 | Agere Systems Inc. | Interdigitaded capacitors |
US7241695B2 (en) | 2005-10-06 | 2007-07-10 | Freescale Semiconductor, Inc. | Semiconductor device having nano-pillars and method therefor |
CN1953181B (en) * | 2005-10-21 | 2010-10-13 | 松下电器产业株式会社 | Analog-digital converter |
WO2007054870A1 (en) | 2005-11-08 | 2007-05-18 | Nxp B.V. | Trench capacitor device suitable for decoupling applications in high-frequency operation |
CN101341576B (en) | 2005-11-08 | 2012-05-30 | Nxp股份有限公司 | Integrated capacitor arrangement for ultrahigh capacitance values |
TW200807729A (en) | 2006-06-02 | 2008-02-01 | Kenet Inc | Improved metal-insulator-metal capacitors |
US8424177B2 (en) | 2006-10-04 | 2013-04-23 | Stmicroelectronics (Crolles 2) Sas | MIM capacitor with enhanced capacitance |
JP2008226998A (en) * | 2007-03-09 | 2008-09-25 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
US8022458B2 (en) * | 2007-10-08 | 2011-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitors integrated with metal gate formation |
FR2965942B1 (en) * | 2010-10-08 | 2013-02-22 | Commissariat Energie Atomique | LIQUID CRYSTAL DISPLAY OF TRANSMISSIVE TYPE IN CMOS TECHNOLOGY WITH AUXILIARY STORAGE CAPACITY |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9685433B2 (en) * | 2013-09-25 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Capacitor device |
KR102163725B1 (en) | 2013-12-03 | 2020-10-08 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
US9640532B2 (en) * | 2014-02-14 | 2017-05-02 | Qualcomm Incorporated | Stacked metal oxide semiconductor (MOS) and metal oxide metal (MOM) capacitor architecture |
CN103972118A (en) | 2014-05-28 | 2014-08-06 | 江阴长电先进封装有限公司 | Forming method of metal cap of wafer-level copper pillar bump structure |
-
2017
- 2017-02-24 FR FR1751499A patent/FR3063387B1/en not_active Expired - Fee Related
-
2018
- 2018-02-22 US US16/488,003 patent/US10957639B2/en active Active
- 2018-02-22 EP EP18709686.2A patent/EP3586360B1/en active Active
- 2018-02-22 WO PCT/FR2018/050418 patent/WO2018154242A2/en unknown
Also Published As
Publication number | Publication date |
---|---|
WO2018154242A2 (en) | 2018-08-30 |
EP3586360B1 (en) | 2021-12-29 |
WO2018154242A3 (en) | 2018-11-22 |
FR3063387A1 (en) | 2018-08-31 |
US10957639B2 (en) | 2021-03-23 |
EP3586360A2 (en) | 2020-01-01 |
US20200135638A1 (en) | 2020-04-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 2 |
|
PLSC | Publication of the preliminary search report |
Effective date: 20180831 |
|
PLFP | Fee payment |
Year of fee payment: 4 |
|
PLFP | Fee payment |
Year of fee payment: 5 |
|
PLFP | Fee payment |
Year of fee payment: 6 |
|
ST | Notification of lapse |
Effective date: 20231005 |