GB2509977A - Packet pre-processing unit which checks received packet validity and redundancy - Google Patents

Abstract

A packet pre-processing unit receives a data packet containing header information and application data, checks the validity of the packet by reference to stored subscription data using header data for the IP destination address, destination port and VLAN tag, checks whether the application data has already been received, and only outputs the packet for further processing if the packet is valid and doesnt contain redundant application data, thereby reducing the load of the memory, bus, and CPU of the computer system.

Description

DESCRIPTION

PREPROCESSING UNIT FOR NETWORK DATA

I. BACKGROUND OF THE INVENTION

A. FIELD OF THE INVENTION

The present invention relates to a preprocessing unit according to the preamble of claim 1, a preprocessing method according to the preamble of claim 11, a computer system including the pre-processing unit according to the preamble of claim 14, and a data storage device comprising configuration data for a config- urable circuit of the preprocessing unit according to the pream-ble of claim 15.

B. DESCRIPTION OF THE RELATED ART

In US patent 8,218,555, US patent application 2010/0241758, US patent 8,131,880, US patent 8,069,102, US patent 7,284,070, US patent application 2012/0089497, US patent application 2007/0255866, US patent 8,130,758, and US patent application 2012/0089694 various preprocessing units are disclosed. These preprocessing units preprocess data packets received from sender computers in a network and then transfer application data (i.e. data destined for an application, preferably a software applica-tion, running on a receiver computer) contained in the data packets to the receiver computer or other components of the re-ceiver computer if the preprocessing unit is a component of the receiver computer, thereby reducing the load on the receiver computer's memory, bus, and CPU. The transferred application data may be in the original format or a different format after decoding. The preprocessing may include the decoding of multiple network protocols, the stripping of header information, the fil- tering of data packets in aocordanoe with time predicates or pa- rameters established by a user, performing data reduction opera-tions such as, for example, the calculation of specific prices in the oase of application data which is financial data. The preprocessing units may include processors or configurable cir-cuits and may even generate and send a response to the sender computer of a data packet.

US patent application 2010/0241758 discloses a preprocessing unit comprising the features of the preamble of claim 1: a data reception means to receive a data packet containing packet in-formation and application data, a relevance checker adapted to determine the relevanoe of said data packet in dependence of said packet information, an output means adapted to output pre- processor output data, and a first control means adapted to con-trol the output of preprocessor output data in dependence of the relevanoe of said data paoket. In this context, preprocessor output data are output data of the processor, packet information is data containing information about said data packet, and ap-plication data information is data containing information of the application data.

In multicast delivery methods, a single sender computer sends data packets to a group of receiver computers. An advantage of these delivery methods is that they oause relatively low traffic if the data packets comprise applioation data to be used by sev-eral of the receiver computers. The preferred multicast delivery methods are based on the user datagram protocol (UDP) having no handshaking dialogues (no confirmation is sent from the receiver computers to the sender computer that a data packets has been received) and are therefore prone to data loss. In order to in-crease the reliability of these and similar delivery methods, identical application data are sent redundantly (at least twice) from one or several sender computers to one or several receiver computers. Disadvantageously, the preprocessing unit disclosed in US patent application 2010/0241758 is not able to discard re-dundant application data resulting in a considerably increased load on the memory, bus, and CPU of the receiver computer.

II. SUMMARY OF THE INVENTION

According to a first aspect of the present invention, a preproc-essing unit comprising a data reception means to receive a data paoket containing packet information and application data, a relevance checker adapted to determine the relevance of the data packet in dependence of the packet information, an output means adapted to output preprocessor output data, and a first control means adapted to control the output of preprocessor output data in depeiidence of Ohe relevance of Ihe dala packeL fur Lher com-prises a redundancy checker adapted to determine the redundancy of the application data, and a second control means adapted to control the output of preprocessor output data in dependence of the relevance of the data packet. In this context, controlling the output of preprocessor output data in dependence of the relevance means that the control is performed in a way ensuring that the preprocessor oitput data depend on the relevance. Thus, the control does not necessarily have to take place at the out-put of the preprocessor, but can take place before. E.g. data of irrelevant data packets may not be forwarded from one prooessing means to the next prooessing mean in the data stream. Corre-spondingly, controlling the output of preprocessor output data in dependence of the redundancy means that the control is per- formed in a way ensuring that the preprocessor output data de-pend on the redundancy. The relevance checker, the first control means, the redundancy checker, and the second control means can be formed as a single means or can be integrated in a single means. Besides, some of these devices can be formed as a single means or can be integrated in a single means, e.g. the first control means and the second oontrol means can form a single control means. Preferably, the preprocessor output data com-prises the application data, decoded or converted application data, or data based on or dependent on the application data in any way, and can comprise further data, e.g. some or all of the packet information or application data information. Preferably, the preprocessing unit does not output any signal, a signal de-pending on the application data, or a signal containing decoded or undecoded application data, if the data packet is not rele- vant and/or if the application data is redundant. In this con-text, a preprocessing unit is a unit which processes received data packets and outputs preprocessor output data via the output means. The preprocessing unit may be a component of a receiver computer, e.g. a network card plugged in a respective computer slot or an external device connected to a receiver computer and may comprise a processor executing instructions stored in a mem-ory of the preprocessing unit, an ASIC circuit or a configurable circuit as for example a FPGA (field programmable gate arrays) circuit. Preferably, the data packet is an Ethernet frame, where the Ethernet frame comprises an IP frame as payload, the IP frame comprises a UDP datagram as the payload, and the payload of the tJDP datagram comprises the application data and the ap- plication data information, and wherein the data packet informa-tion is contained in the header of the Ethernet frame, the header of the IP frame, and the header of the UDP datagram.

Preferably, the payload of the 1JDP datagram has a structure spe-cific to the computer system and the preprocessing unit, so that the preprocessing unit can easily distinguish the application data from the application data information. Preferably, the ap-plication data information is contained in a header followed by a series of messages, where the series of messages forms the ap-plication data, each message contains a message number, and the application data information includes the message number of the first message contained in the UDP datagram and/or the count (total number) of messages contained in the UDP datagram or, al-ternatively, the message numbers of all messages contained in the UDP datagram. Input/output or I/O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the processing unit either directly or through inter-vening I/C controllers. Network adapters may also be coupled to the system to enable the data processing system to become cou-pled to other data processing systems or remote printers or storage devices through intervening private or public networks.

Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters. A particular area of application of the processing unit is in the real-time proc-essing of financial data such as option feeds.

Tn a preferred embodiment, the preprocessing unit comprises at least one decoder adapted to decode the application data and to generate decoded application data. Preferably, several decoders each adapted to decode the application data and to generate de-coded application data are provided. The application data may contain messages with financial data like the prices of shares at a given time in a given format, e.g. ASCI format, which may be decoded (converted) to a different format, e.g. binary for-mat, used by the application(s) running on the receiver computer and easier to process, thereby further reducing the load on the memory, bus, and CPU of the computer system. In addition, only a part of the application data may be decoded or different parts of the application data may be decoded differently.

In a further development of the preferred embodiment, the pre-processing unit comprises an addresser adapted to address said decoded application data to a storage area of a memory. Prefera- bly, the memory is a RAM of a computer. The software applica-tion(s) running on the computer presume(s) that specific data is stored in the specified storage area of the memory speeding up the processing of the application data.

In a preferred embodiment, the preprocessing unit comprises at least one buffer adapted to send a fill level signal to the sec-ond control means, and the second control means is adapted to control the sending of the application data to the at least one buffer or the receipt of the application data by the at least one buffer in dependence of the fill level signal. Both alterna-tives are eguivalent. Preferably, several buffers each adapted to send a fill level signal to the second control means are pro-vided and the second control means is adapted to control the sending of the application data to one buffer of the several buffers or the receipt of the application data by one buffer of the several buffers in dependence of the fill level signals.

Thus, an overflow of the buffers can be prevented.

In yet another preferred embodiment, the relevance checker is adapted to determine the relevance of the data packet received from a first incoming line in dependence of the packet informa-tion, and the preprocessing unit comprises a further relevance checker adapted to determine the relevance of a further data packet received from a second incoming line in dependence of the packet information of the further data packet. Thus, the two relevance checker can check the relevance of data packets from two incoming lines in parallel.

In yet another preferred embodiment, the relevance checker com-prises at least one subscription checker adapted to determine whether the data packet originates from a subscribed sender and a delayer adapted to delay the transfer of the application data, while the relevance of the data packet is determined. In order to determine the relevance of a data packet, the subscription checker verifies whether an entry indicating that the data pack-et is relevant is present in a subscription memory. Preferably, the relevance checker comprises at least two subscription check-ers and switches between the at least two subscription checkers, wherein the packet information is alternately sent to one of the subscription checkers. The subscription checkers use a search procedure which takes several clock cycles in order to check whether an entry in the subscription memory already exists. By providing at least two subscription checkers working in paral-lel, the delay of the processing unit can be minimized.

In yet another preferred embodiment, the data packet contains application data information, the redundancy checker comprises an information memory, and the redundancy checker is adapted to store identification data depending on the application data in- formation in the information memory and to determine the redun-dancy of the application data in dependence of identification data of data packets received before and stored in the informa-tion memory. Preferably, a second data packet comprising the same application data as a first data packet received before also comprises the same application data information as the first data packet, wherein only data packets comprising identi-cal application data also comprise identical application data information. Either the application data of the second data packet or the first data packet is redundant. Usually, the ap-plication data of the second data packet is defined as redundant application data. In order to verify whether the application data of the second data packet is redundant, the application data of the first data packet can be compared to the application data of the second data packet, or the application data informa-tion of the first data packet can be compared to the application data information of the second data packet. Comparing only the application data requires fewer resources.

Tn a further development of the last preferred embodiment, the identification data also depends on the packet information. Tak-ing into account at least a part of the packet information, the verification of the red-indancy is unambiguous.

In yet another preferred embodiment, the preprocessing unit in-cludes a configurable circuit, and the relevance checker and the redundancy checker are formed by configured elements of the con-figurable circuit. FGPA circuits are the preferred configurable circuits. As specialized hardware circuits, configurable cir-cuits are very fast. In addition, a preprocessing unit in the fcrm of a configurable circuit can be easily manufactured in small quantities.

Tn a further development of the preferred embodiment, the pre-processing unit comprises a nonvolatile memory containing the configuraLion daLa and a daLa loader adapLed Lo Lransfer Lhe configuration data. The configuration data is transferred to configuration memories defining the configuration of the config-urable circuit. Preferably, the nonvolatile memory also contains handling data which is transferred to one or several handling memories by the data loader.

According to a second aspect of the present invention, a preprocessing method comprises the following steps: -receiving a data packet containing packet information and ap-plication data; -determining the relevance of the data packet in dependence of the packet information; -controlling the output of preprocessor output data in depend-ence of the relevance of the data packet; -determining the redundancy of the application data; and -controlling the output of preprocessor output data in depend-ence of the redundancy of the application data.

In a preferred embodiment of the preprocessing method, the data packet contains application data information, identification data based on the application data information is stored, and the redundancy of the application data is determined in depend-ence of the identification data of data packets stored before.

In yet another preferred embodiment of the preprocessing method, the identification data also depends on the packet information.

According to a third aspect of the present invention, a computer system including a preprocessing unit comprising a data reception means to receive a data packet containing packet in-formation and application data, a relevance checker adapted to determine the relevance of the data packet in dependence of the packet information, and an output means adapted to output pre-processor output data, a first control means adapted to control the output of preprocessor output data in dependence of the rel-evance of the data packet further comprises a redundancy checker adapted to determine the redundancy of the application data and a second control means adapted to control the output of preproc- essor output data in dependence of the redundancy of the appli-cation data.

According to a fourth aspect of the present invention, a data storage device comprises configuration data for a configur-able circuit of a preprocessing unit, wherein the configurable circuit comprises a data reception means to receive a data pack- et containing packet information and application data, a relev-ance checker adapted to determine the relevance of the data -10 -packet in dependence of the packet information, and an output means adapted to output preprocessor output data, a first con-trol means adapted to control the output of preprocessor output data in dependence of the relevance of the data packet further comprises a redundancy checker adapted to determine the redunda-noy of the application data, and a second oontrol means adapted to control the output of preprocessor output data in dependence of the redundancy of the application data, when the configurable circuit is configured by the configuration data.

In general, a single processing unit can comprise any combina- tion of features of the preferred embodiments and further devel-opments. Correspondingly, the preprocessing method, computer system, and data storage device can comprise any combination of the respective features.

III. BRIEF DESCRIPTION OF ThE DRAWINGS

A detailed desoription of the invention is given in the follow-ing drawings in which: FIG. 1A shows the schematic structure of an Ethernet packet; FIG. l shows the schematic structure of an IP frame; FIG. 10 shows the schematic structure of an UDP datagram; FIG. 3 shows the architecture of a computer comprising a pre-processing unit; FIG. 4 shows the structure of the preprocessing unit 6; FIG. 5 shows the structure of a FGPA circuit included in the preprocessing unit; and FIG. 6 shows the structire of a relevance checker which is a component of the FGPA circuit.

-11 -

TV. DETAILED DESCRIPTION OF THE INVENTION

FIG. lA shows the schematic structure of an Ethernet packet re-ceived by a preprocessing unit 6. The basic structure of the Ethernet packet is standardized. Two consecutive Ethernet data packets are separated by an inter-frame gap IFG (at least 12 Byte) . Each Ethernet packet includes a preamble p (7 Byte) , a start of frame delimiter SFD (1 Byte), an Ethernet frame (E-H+E-Ph), and an Ethernet frame footer E-F (4 Byte) . The Ethernet frame is composed of an Ethernet frame header F-H and an Ethernet frame payload E-PL. The Ethernet frame header F-H com- prises a media access destination address MAC-D (6 Byte), a me-dia access source address MAC-S (6 Byte), and a VLAN tag (4 Bytes) . The Ethernet frame payload has a size between 38 and 1500 Byte.

FIG. lB shows ihe schemaLic sirucLure of an IP frame. The IP frame (IPv4) forms the payload of the Ethernet frame and com-prises an IP frame header IP-H (40 Byte) and an IP frame payload IP-PL. The IP frame header IP-H comprises a IP destination ad- dress IP-D (4 Byte), a IP source address TP-S (4 Byte), and sev- eral further fields summarized as IP-M (32 Byte) and not de-scribed in more details as the exact structure is not relevant in the context of the present invention.

FIG. lC shows the schematic structure of an UDP datagram. The UDP datagram forms the payload of the IP frame and comprises a UDP datagram header UDP-H and a UDP datagram payload tJDP-PL. The UDP datagram header UDP-H comprises a source port address s-P (2 Byte), a destination port address B-P (2 Byte), a length field

L, and a checksum field CS (2 Byte)

-12 -The data in the Ethernet payload oan be unambiguously identified by the destination IP address IP-D, the VLAN tag, and the desti-nation port address D-P. The IP destination address IP-D, the VIJPN tag, and the destination port address D-P are referred to as packet information hereinafter. The format of the UDP data-gram UDP-PL payload is not standardized and is specific for the present application, and comprises a sequence number field SN, a message number field MN, and one or several messages Ml, M2, M3, and Ni, wherein each message includes a message number. The se- quence number field SN and the message number field MN are re- ferred to as application data information hereinafter. The mes-sages Ml, N2, Ml, and Mi are referred to as application data hereinafter. The message sequence number field SN specifies the number of the message sequence or the number of the first mes-sage of the respective UDP datagram, and the message number MN specifies the count (total number) of messages in the respective UDP datagram. For example, if five messages are contained in a first UDP datagram, the respective sequence number is SN=l, the respective number of messages is MN=5, if three messages are contained in a second UDP datagram subsequent to the first LJDP datagram, the respective sequence number is SN=2, the respective number of messages is MN=3, alternatively, the respective se-quence number can be SN=6 and the respective number of messages can be MN=3. Both numerations are unambiguous. Only one of the alternatives can be used if there is no further field in the UDP datagram specifying the alternative used.

FIG. 2 is a flowchart of a preprocessing method. In step Si, an Ethernet frame DATIIA is received. In step S2, it is verified whether the Ethernet frame DATA is corrupt or not. if the Ethernet frame DATAA is corrupt, the further processing of the DATIIA frame is not required and can be ended. If the Ethernet frame DATIIA is not corrupt, the IF destination address IF-D and the VLAN tag which are summarized as Cl data and form part of -13 -the packet infcrmation and the tJDP datagram DGA are extracted from the Ethernet frame DATAA in step 53. A data area 02 com-prising the destination port D-P, the sequence number SN, and the message number MN is extracted from the tJDP datagram DGA in step 84. The destination port S-P also forms part of the packet information, whereas the sequence number SN and the message num-ber MN form the application data information. In step 55, it is verified whether the tJDP datagram DGA is relevant on the basis of a comparison of the packet information with stored data. The UDP datagram is relevant if the stored data includes an entry which indicates that the UDP datagram is relevant. This entry is identical to the packet information or includes the packet in-formation. If the UDE datagram DGA is not relevant, the further processing of the Ethernet frame DATAA is not required and can be ended. If the UDP datagram DGA is relevant, identification data IDA is generated based on the Cl data and 02 data (based on the IF destination address IP-D, the VLAN tag, the destination port D-P, the sequence number SN, arid the message number MN) in step 86. In step S7, it is verified whether the UDP datagram DGA is corrupt or not. If the UDP datagram DGA is corrupt, the fur-ther processing of the Ethernet frame DATAA is not required and can be ended. If the UDP datagram DGA is not corrupt, it is verified whether the UDP datagram DGA is redundant in step 38 on the basis of a comparisons of the identification data IDA with stored data. The UDP datagram is redundant if the stored data includes an entry which is identical to the identification data TDA. If the UDP datagram DGA is redundant, the further process-ing of the Ethernet frame DATAA is not required and can be ended. If the UDP dataqram DGA is not redundant, the identifica-tion data IDA is stored. The stored identification data IDA is used in order to verify the redundancy of later datagrams. In step 810, the UDP dataqram is decoded as DD (converted in DD) and addressed to a storage area of a RAM (see FIG. 3) . In step 511, the decoded UDP datagram DD is output. In general, the checks in step S2, 55, 37, or SB require the receipt of all nec- -14 - essary data or a complete UDP datagram which usually takes sev- eral clock cycles. The UDP datagram is processed in a specu-lative stream mode, wherein a following step can start or even be finished before a previous step has ended, wherein the re- ceived data of a UDP datagram may be forwarded and further proc-essed before all data of the JDP datagram has been reoeived, and wherein the data resulting from a later step may be discarded if the result of a check started in an earlier step is negative. By starting a following step before the previous step is finished, the delay due to the preprooessing method is minimized. The steps 51 to 511 can also be performed in a different order.

The processing method can be executed by an entirely hardware embodiment, an entirely software embodiment or an embodiment containing both hardware and software elements. A software em-bodiment can include but is not limited to firmware, resident software, microcode, etc. Furthermore, the processing method can take the form of a computer program product accessible from a computer-usable or compiter-readable medium providing program code for use by or in connection with a computer or any instruc-tion execution system. A computer-usable or computer readable medium oan be any apparatus that can contain, store, communica- te, propagate, or transport the program for use by or in connec- tion with the instruction execution system, apparatus, or de- vice. The medium can be an electronic, magnetic, optical, elec-tromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (RON), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk -read only memory (CD-ROM) , compact disk -read/write (CD-R/W) and DVD. Hereinafter, the functioning of a preprocessing -15 - unit executing the preprocessing method is explained with refer-ence to the steps in the flowchart FIG. 2.

FIG. 3 shows the architecture of a computer. The computer com-prises several components including an input/output device 1, a Cpu 2, a ROM 3, a RAM 4, a bus connection controller 5, a pre-processing unit 6, a further processing unit 7, a main bus 8, an expansion bus 9, and two incoming lines 10 and 11. The in-put/output device 1 communicates with a keyboard, a mouse and a monitor via the connection 85. The input/output device 1, the Cpu 2, the ROM 3, and the RAM 4 are directly connected to the main bus 8 and can send and/or receive data to/from other compo-nents of the computer. The preprocessing unit 6 and the further processing unit 7 are directly connected to the expansion bus and can send and/or receive data to/from other components of the computer. The bus connection controller 5 controls the data ex- change between the main bus 8 and the expansion bus 9 and en-ables the data communication between the components 1, 2, 3, and 4 directly connected to the main bus 8 and the components 6 and 7 directly connected to the expansion bus 9. The expansion bus 9 is a PCI (Peripheral Component Interconnect) Express bus. Corre-spondingly, the bus connection controller 5 is a PCI Express controller and the preprocessing unit 5 and the processing unit 7 which might be a graphics card are PCI Express cards. The functioning and interaction of the components 1, 2, 3, 4, 5, 7, 8, and 9 is known from the prior art and is therefore not de-scribed in detail. The computer executes one or several software applications which use application data contained in input data.

The application data is redundantly sent twice by a multicast delivery method by two different senders (one sender connected to the data line 10 and the other sender connected to the data line 11) . The redundant data must not necessarily be sent by two different senders on two different lines. Redundant data may also be sent on a single line. By sending identical application -16 -data twice (once via each data line), the probability of data loss which is critical for any multicast delivery method is con- siderably reduced. The maximum delay between receipt of redun- dant application data is limited to a maximum delay. The incom-ing data lines 10 and 11 are Ethernet lines and the input data is packed in Ethernet frames. The preprocessing unit 6 which is an inbuilt component of the computer receives the Ethernet frames (step 51), performs the steps 52 to 510 with the Ethernet frames and outputs the decoded application data DD on the line 12 (step Sli) which is addressed to a storage area of the RAM 4.

Then, the decoded application data DD is transferred via the ex-tension bus 9, the connection controller 5, and the main bus 8 to the CPU 2 or to the RAM 4 where it is disposable (available) to the respective software application. By forwarding only rele-vant decoded data, the traffic on the buses 8, 9, and the data to be saved in the RAN and to be processed by the CPU 2 is re- duced. The software application is adapted to the decoded ap- piioaticri data DD of the preprocessing unit 6, so that the proc- essing of the decoded application data DU requires less process-ing steps of the CPU 2 than corresponding undecoded data.

The preprocessing unit 6 executing the processing method can be an entirely hardware embodiment or an embodiment containing both hardware and software elements. As an embodiment containing both hardware and software elements, the preprocessing unit 6 can in-clude at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to re- duce the number of times code must be retrieved from bulk stor-age during execution. An entirely hardware embodiment of the preprocessing unit 6 is described hereinafter.

-17 - FIG. 4 shows the structure of the preprocessing unit 6 comprisi- ng a nonvolatile data memory 14, a data loader 15, a PCI inter- face 16, a FGPA circuit 18 and Ethernet interfaces 19, 20. Non-volatile data memories, data loaders, PCI interfaces, and Ethernet interfaces are known from the state of the art. As far as the devices 14, 15, 16, 19, and 20 differ from known devices, a person skilled in the art could realize such devices from the description of the tasks performed by the devices. Therefore, the devices 14, 15, 16, 19, and 20 do not have to be explained in detail. The FGPA circuit 18 is described in detail with ref-erence to FIG. 5 and FTG. 6. The FGPA (field programmable gate arrays) circuit 18 is an electronic circuit programmable by con-figurable electrical interconnections and can perform multiple logic functions in accordance with the configuration data in volatile local configuration memories and handling data in hand-ling data memories of the FGPA circuit 18. The configuration memories present in any FGPA circuit are obvious to a person skilled in the art arid are therefore riot shown. In this context, configuration data are data which define the configuration of the electrical interconnections of the FGPA circuit 18, and han-dling data are data concerning the handling (processing) of the data received by the preprocessing unit 6. Before the FGPA cir- cuit 18 can perform any desired logic functions, the correspond-ing configuration data have to be written in the volatile local configuration memories and the handling data have to be written in the handling data memories. For this purpose, the data loader reads out the configuration data and handling data in the nonvolatile data memory 14 and transfers the configuration data to the volatile local configuration memories and the handling data to the handling data memories. The configuration data and application data in the nonvolatile data memory 14 can be ex- changed by writing new data via the write-in line 13 in the non- volatile data memory 14. In order to write new data in the non-volatile data memory 14, the preprocessing unit 6 is removed from the computer and the line 13 is connected to a data loading -18 -device (not shown) . Alternatively, the line 13 can be connected to the PCI bus 9 so that new data can be written in the nonvola-tile data memory 14 without removing it. The preprocessing unit 6 receives Ethernet frames via the data lines 10 and 11 at the Ethernet interfaces 19 and 20 from two sender computers. The Ethernet interfaoes 19 and 20 forward the Ethernet frames to the FGPA circuit 18 via the lines 21, 22. The FGPA circuit 18 re-ceives the Ethernet frames (step Si), performs the steps S2 to S with the Ethernet frames and outputs the decoded application data DD via the line 49 to the PCI interfaoe 16. The PCI inter-face 16 outputs the decoded application data DD via the line 12.

FIG. 5 shows the structure of the FGPA circuit 18 included in the preprocessing unit 6. The FGPA circuit 18 comprises two rel-evance oheckers 23 and 24, and a redundancy ohecker 29, six buffers 37, 38, 39, 90, 91, and 92, three decoders 43, 44, and 45, and an addresser 96. The redundancy checker 29 comprises a data comparator 85, an information memory 17, a controller 84, and buffers 86, 87, 88, 89. Buffers, decoders, data comparators, information memories, controllers, and addressers are known from the state of the art. As far as the devices 37, 38, 39, 43, 44, 45, 85, 17, 84, 85, 86, 87, 88, 89, 90, 91, 92, and 96 differ from known devices, a person skilled in the art could realize such devices from the description of the tasks performed by the devices. Therefore, the devices 37, 38, 39, 43, 44, 45, 95, 17, 84, 85, 86, 87, 88, 89, 90, 91, 92, and 96 do not have to be explained in detail. The relevance checkers 23 and 24 are de-scribed in detail in FIG. 6. In general, the relevance checkers 23, 24 are clocked with a lower frequency and have a lower data path width than the redundancy checker 29, the six buffers 37, 38, 39, 90, 91, and 92, three decoders 43, 44, and 45, and the assigner 96. Preferably, the relevance checkers 23, 24 are clocked with a frequency of 160 MHz and have a data path width of 64 bit, whereas the redundancy checker 29, the three buffers -19 - 37, 38, and 39 and three decoders 43, 44, and 45 are clocked with a frequency of 250 MHz and have a data path width of 128 bit. The relevance checker 23 receives an Ethernet frame DATIA via the line 21 (step Si), checks whether the Ethernet frame DATAA is corrupt (step 32), extracts the destination IP address IP-D and the VLIN tag summarized as Cl data, the data area C2 comprising the destination port C-F, the sequence number SN, and the message number MN, and the tJDP datagram DGA of the Ethernet frame DATAPI (step 53+54), decides whether the Ethernet frame DATIA is relevant for the software application(s) running on the computer by means of the packet information (comprising the des-tination IP address IP-D, the VLAN tag, and the destination port address D-P) of the Ethernet frame DATAA or not (step 55), gen-erates the identification data IDA (step 56), and checks whether the UDP datagram DGA is corrupt or not (step 57) . If the Ethernet frame DATAA is relevant for the software application(s) and not corrupt, and the UDP datagram DGA is not corrupt, the relevance checker 23 generates arid outputs identification data IDA on the line 26 and the UDP datagrarn DGA of the Ethernet frame DATAA on the line 25. The identification data comprises an identifier based on the destination IP address IP-D, the VLAN tag, the destination port address D-P, the sequence number SN, and the number of messages N, an indication of the decoder(s) 43, 44, and 45 to be used in order to decode the UDP datagram DGA and a relative time stamp indicating when the identification data was created in order to assess the performance of the FGPA circuit 18. The identifier is identical for Ethernet frames com-prising identical application data. The UDP datagrams have a format which can be identified by the respective packet informa-tion and application data information. The decoder 43, 44, and may decode data from a specific format, e.g. ASCII format, into data in another specific format, e.g. binary format, which can be easily processed. In addition, the decoders 43, 44, and may only decode certain parts of the payload, e.g. the mes- sage data Ml, 142, M3,... Mi. The indication indicating which de- -20 - coder(s) 43, 44, and 45 is (are) suitable for decoding UP data-grams DGA is based on the packet information and application data information. If the Ethernet frame DATAA is corrupt or con-tains no relevant application data, or the UDP datagram DGA is corrupt, the relevance checker 23 discards the Ethernet frame DATIA (does not output any signal, a signal depending on the packet information or application data information or a signal containing decoded or undecoded packet information or applica- tion data information on line 26 and/or any signal, a signal de-pending on the application data or a signal containing decoded or undecoded application data on line 25) . Analogously, the relevance checker 24 which is constructed identically to the relevance checker 23 receives an Ethernet frame DATAB via the line 22, processes the Ethernet frame DATAB, generates and out-puts the respective identification data 1DB on the line 28 and the UDP datagram DGB of the Ethernet frame DATAB on the line 27 or discards the Ethernet frame DATAB. The redundancy checker 29 receives the identification data IDA and the corresponding UDP datagram DGA via the lines 26 and 25, respectively, and buffers the identification data IDA in the buffer 87 and the 1LJDP data-gram DGB in the buffer 86. Analogously, the redundancy checker 29 receives the identification data 1DB and the corresponding UDP datagram DGB via the lines 28 and 27, respectively, and buffers the identification data 1DB in the buffer 89 and the UDP datagram DGB in the buffer 88. The buffering allows the redun-dancy checker 29 to finish the processing of the data received before. The information memory 17 of the redundancy checker 29 contains entries of identification data received before. Each of the buffers 37, 38, and 39 is associated with one of the decod-ers 43, 44, and 45 (i.e., the data stored in the buffers 37, 38, and 39 is sent to only one of the decoders 43, 44, and 45), re-spectively. The buffers 37, 38, and 39 continuously send fill level signal fi, f2, and f3 indicating the fill level of the re- spective buffer 37, 38, and 39 to the controller 84. The con- trolley 84 sends control signals to the buffers 86 and 87 in or- -21 -der to enable the buffers 86 and 87 to output the UDP datagram DGA and identification data IDA, respectively. The data compara-tor 85 reoeives the identification data IDA and oompares the identification data IDA with the entries in the information mem- ory 17 (step SB) . If the information memory 17 contains no iden-tical entry, the data comparator 85 sends a signal indicating that the information memory 17 contains no identical entry to the controller 84 and stores the identification data IDA in the information memory 17 (step S9) . If the (oldest) identification data entry in the information memory 17 is older than the maxi-mum possible delay between identical identification data IDA, the redundancy checker 29 deletes the first (oldest) identifica-tion data entry in the information memory 17. Ihe controller 84 receives the signal indicating that no identical application data has been received before and the fill level signals fl, f2, and f3 indicating the fill level of the respective buffers 37, 38, and 39 and sends a write signal wl, w2, or w3 via one of the write signal lines 31, 32 or 33 to one of the buffers 37, 38, or 39 associated with a suitable decoder 43, 44, or 45. If there are several decoders 43, 44, 45 suitable for the decoding of the UDP datagram DGA, a write signal wl, w2, w3 is sent to the buffer 37, 38, or 39 associated with a suitable decoder 43, 44, or 45 and having the lowest fill level. The redundancy checker 29 outputs the UDP datagram DGA on the line 30 which is con-nected to the inputs of all buffers 37, 38, and 39. The buffer 37, 38, or 39 receiving the write signal wi, w2, w3 is enabled to read the DSP datagram DGA. If the information memory 17 con- tains a packet information entry indicating that identical ap-plication data has been received before, the data comparator 85 sends a signal indicating that identical application data has been received before to the controller 84 and the controller generates no write signal wl, w2, or w3, so that none of the buffers 37, 38, or 39 is enabled to receive the UDP datagram DGA. Then, the controller 84 switches to the data received from the other relevance checker 24 by sending control signals to the -22 -buffers 88 and 89 in order to enable the buffers 88 and 89 to output the UDP datagram DGB and identification data 1DB, respec-tively. The relevance checker 24 prcoesses the UDP datagram DGB and identification data 1DB analogous to the UDP datagram DGA and identification data IDA. In temporal terms, the switching is possible as the data path width of the redundancy checker 29 is twice as high as the data path widths of the relevance checkers 23, 24 and the frequency of the redundanoy checker 29 is consid-erably higher than the frequencies of the relevance checkers 23, 24. The deccders 43, 44, and 45 detect whether a JDP datagram DGIk is stored in the respective buffer 37, 38 or 39 and read out the UDP datagram DGA. The respective decoder 43, 44 or 45 de-codes the UDP datagram DGA (step 10) and outputs the decoded UDP datagram SD via the line 46, 47, or 48 to the respective buffer 90, 91, or 92. The addresser 96 reads out the data stored in the buffers 90, 91, or 92 consecutively and continuously using a round robin procedure, wherein the data stored in the buffers 90, 91, arid 92 is read out only if the data has a minimum size of several Bytes or the complete decoded UDP datagram is stored in the respective buffer 90, 91, or 92. Alternatively, the buff-ers 90, 91, or 92 can generate fill level signals and send the fill level signals to the addresser 96, and the addresser 96 can read out the data stored in the buffer 90, 91, or 92 with the highest fill level. The addresser 96 addresses the data read out from the buffers 90, 91, or 92 (the decoded UDP datagrams DD) to a specified storage area of the RAM 4 (see FIG. 3) and outputs the data (the decoded UDP datagrams DD) on the line 49 (step 311) FIG. 6 shows the structure of the relevance checker 23 which is a component of the FGPA circuit 18. The relevance checker 23 comprises a frame data extractor 50, a write controller 54, a UDP datagram data extractor 55, two subscription checker 60, 61 each including a subscription memory 63 and 64, respectively, a -23 - delayer (pipeline) 62, a multiplexer 71, a decoder 73, a data-gram checker 74, a controller 75, and two buffers 80, 81. Frame data extractors, write controllers, datagram data extractors, subscription checkers, subscription memories, delayers (pipe-lines), multiplexers, decoders, datagram checkers, controllers, and buffers are known from the state of the art. As far as the devices 23, 50, 54, 55, 60, 61, 63, 64, 62, 71, 73, 74, 75, 80, and 81 differ from known devices, a person skilled in the art could realize such devices from the description of the tasks performed by the devices. The frame data extractor 50 receives the Ethernet frame DATAA from the incoming line 21 (step Si), checks whether the Ethernet frame DATAA is corrupt or not using the data in the CRC field (step 52), extracts the packet infor-mation comprising the destination IP address IP-D and the VIJAN tag summarized as Cl data and the UDP datagram DGA (step 53) and sends the Ci data via the line 51 to the write controller 54 and the UDP datagram via the output line 52 to the datagram data extractor 55. If the Ethernet frame DAT is corrupt, the Ethernet frame extractor sends an error signal cr1 via the line 53 to the controller 75. As the check requires the receipt of all bits of the Ethernet frame DATAA, the check might be fin-ished after some of the following steps. The write controller 54 receives the Cl data from the output line 51 and outputs the Cl data on the line 57 and a single write signal w4 or w5 via the respective line 56 or 57 to the respective subscription checker or 61. The datagram data extractor 55 receives the UDP data-gram data DGA, extracts a data area 02 of the UDP datagram DGA containing the destination port D-P, the sequence number SN, and the message number MN and having a length of several Bytes, and the UDP datagram DGA. The position and the format of the se-guence number SN and the message number MN depend on the VLAN tag, IP-D and D-P. The datagram data extractor 55 sends the C2 data containing the destination port D-P, the sequence number SN, and the message number MN via the output line 82 to both subscription checkers 60, 61 and transfers the UDP datagram DGA -24 - via the line 59 to the delayer 62. However, only the subscrip- tion checker 60 or 61 receiving the write signal w4 or w5 is en-abled to receive the Cl data and the C2 data. To ensure that both subscription checkers are egually loaded and not over-loaded, the write signal w4 is sent out if the last write signal sent out by the write controller 54 is the write signal w5 and vice-versa. By a binary search for subscription data in the sub-scription memory (lookup table) 63 and 64, respectively, the subscription checker 60 or 61 receiving the write signal w4 or w5 checks whether the respective DGA is relevant or not (step 5) . The subscription memories 63 and 64 are the handling data memories mentioned before. Correspondingly, the subscription data are handling data mentioned before. The subscription checker 60 or 61 searches for an entry which is identical to the packet information or includes the packet information. This search usually takes longer than the receipt of the complete Ethernet frame DATAA, but not twice as long as the receipt of the complete Ethernet frame DATAA. Therefore, a single subscrip-tion checker could be overloaded. By using two subscription checkers 60 and 61 in parallel, an overload can be prevented. In addition, the subscription checkers 60 and 61 check continuously whether the subscription data in the subscription memory 63 and 64, respectively, is corrupt or not using check data, e.g. one or several parity bits, stored in the respective subscription memory 63 and 64, respectively (The check data are also handling data) . If the JDP datagram DGA is not relevant or subscription data is not correct, the subscription checker 60 and 61 send a control signal vl and v2, respectively, indicating that UDP datagram DGA is not relevant or subscription data is not correct to the controller 75. If the JDP datagram DGA is relevant and the subscription data is correct, the subscription checker 60 and 61 send a control signal vi and v2, respectively, indicating that UDP datagram DGA is relevant and subscription data is cor-rect to the controller 75. Additionally, the subscription checker 60 sends the Cl data and 02 data via the line 66 and a -25 -write signal w6 via the line 65 and the subscription checker 61 sends the 01 data and 02 data via the line 69 and a write signal w7 via the line 68 to the multiplexer 71, respectively. The write signal w6 and w7 enable the multiplexer 71 to receive the 01 data and 02 data from the subscription checker 60 and sub-scription checker 61, respectively. The multiplexer 71 receives the Cl data and 02 data and outputs the Cl data and 02 data via the line 72 to the decoder 73. The decoder 73 decodes the Cl and 02 data (the decoded Cl data and 02 data is referred to as iden-tification data IDA, step S6), and outputs the identification data IDA via a line 76 to the buffer 80. The delayer 62 delays the UDP datagram DGA by several clock cycles and outputs the UDP datagram DGA via the line 83 to the datagram checker 74. The datagram checker 74 checks whether the UDP datagram DGA is cor-rupt or not using the data in the CS field and/or the L field of the UDP datagram header UDP-H and/or the length of the UDP data-gram DGA and outputs the UDP datagram DGA via the line 79 to the buffer 81 (step 57) . If the UDP datagram DGA is corrupt, the da-tagram checker 74 sends an error signal cr2 to the controller 75. If the controller 75 receives an error signal cr1 from the frame extractor 50 indicating that the Ethernet frame DATAA is corrupt, an error signal from the datagram checker 74 indicating that the UDP datagram DGA is corrupt, or a control signal vi or v2 from the subscription checker 60 and 61, respectively, indi-cating that the subscription data is corrupt or that the UDP datagram DGA is not relevant, the controller 75 sends a reset signal rsl w8 via the line 77 to the buffer 80 and a reset sig-nal rs2 via the line 79 to the buffer 81. The buffer 80 receives the identification data IDA from the decoder 73. If the buffer receives no reset signal rsl, it outputs the identification data IDA on the line 27. If the buffer 80 receives a reset sig-nal rsl, the buffer 80 is reset, the identification data IDA is discarded, and the buffer 80 does not output the identification data IDA. The buffer 81 receives the UDP datagram DGA from the datagram checker 74. If the buffer 81 receives no reset signal -26 -rs2, it outputs the UDP datagram DGA on the line 28. If the buffer 81 receives a reset signal rs2, the buffer 81 is reset, the UDP datagram DGA is discarded, and the buffer 80 does nct output the UDP datagrarn DGA.