JP2000231062A - Endoscopic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct cable length with inexpensive constitution by reducing the number of parts. SOLUTION: A CCD 16 is driven according to a driving signal from an SSG 32 through a delay circuit 33, etc. Then, an image pickup signal from the CCD 16 is converted into a video signal by a correlative double sampling(CDS) circuit 24 driven according to a sample-hold signal given from the SSG 32 through the circuit 33, and outputted after it is converted into the video signal displayed on a monitor through an A/D converter circuit 25, a video signal processing circuit 34 and a digital encoder 35. At such a time, by correcting the phase of the image pickup signal and the sample-hold signal given to the circuit 24 by the circuit 33, the cable length is corrected. Since the circuit 33 is constituted to be assembled in a digital signal processor for processing a video signal 21 in which the circuit 34, etc., are housed, the number of parts is reduced and the device is constituted at a low cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a means for correcting a signal delay caused by a signal cable connected to an image pickup device provided at an end of an endoscope insertion portion or detachably attached to an endoscope eyepiece. The present invention relates to an endoscope device having features.

[0002]

2. Description of the Related Art In recent years, endoscopes capable of observing a subject inside a body cavity or a duct by inserting an elongated insertion portion into a body cavity or a duct have been widely used. Such an endoscope includes, for example, a CCD as an image pickup means for picking up a subject image at the distal end of the insertion section, and a signal cable extending from the CCD is connected to the inside of the insertion section and the proximal end side of the insertion section. It is inserted through the provided operation unit, extends from the operation unit, and is electrically connected to an external video processor. The video processor supplies a drive signal to the CCD via the signal cable, converts an image signal obtained from the CCD via the signal cable into a video signal, and renders a subject image on a monitor device or the like. ing.

However, when the signal cable is long, the drive signal and the imaging signal cause a delay during transmission of the signal cable, and are received in the video processor at the timing of transmitting the drive signal. There is a possibility that the timing of the imaging signal is delayed, and the video signal cannot be normally reproduced.

Therefore, for example, in Japanese Patent No. 2694753, a delay line for adjusting the phase of a drive signal and a sample-and-hold signal for sampling a received image signal is provided to correct a delay caused by a signal cable length. Means are shown.

[0005]

However, Japanese Patent No. 2694753 discloses a delay line dedicated to the cable length correcting means, in order to constitute a means for correcting the cable length, that is, the correction for the delay caused by the signal cable length. IC
Because electronic components such as are added to the video processor,
Accordingly, there is a problem that the cost increases due to an increase in the number of parts. The present invention has been made in view of the above circumstances, and has as its object to provide an endoscope apparatus capable of performing cable length correction with an inexpensive configuration by reducing the number of components.

[0006]

In order to achieve the above object, the present invention provides a means for generating a first drive signal for driving an imaging means incorporated in an endoscope or detachably connected thereto, Video signal extracting means for obtaining a first video signal included in the image signal obtained by the image capturing means; and driving the video signal extracting means to cause the video signal extracting means to extract the first video signal from the image signal. Means for generating a second drive signal for controlling the timing of obtaining the second video signal, and a first processor storing at least a part of a circuit for obtaining a second video signal that can be monitored and displayed from the first video signal. An endoscope device having a delay circuit for delaying at least a part of signals included in the first drive signal and the second drive signal stored in the first processor. Characteristic It is.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 relate to a first embodiment of the present invention. FIG. 1 is a block diagram showing an entire configuration of an endoscope apparatus, and FIG. 2 is a block diagram showing a configuration of a delay circuit.

As shown in FIG. 1, an endoscope apparatus 1 according to the present embodiment includes an endoscope 2 which is inserted into a body cavity or a duct to obtain an image signal corresponding to a subject image. A video processor 3 is provided to obtain a video signal that can be displayed on a monitor from an image signal obtained by the endoscope 2.

The endoscope 2 has an elongated insertion portion 11 for insertion into a body cavity, a duct, or the like, and is provided continuously with a base end side of the insertion portion 11 so that the endoscope 2 can be gripped and operated. Operating unit 12, a signal cable 13 extending from the side of the operating unit 12 and connected to the video processor, and provided at an end of the signal cable 13 and detachably connected to the video processor 3. And an objective optical system 15 provided at the tip of the insertion section 11 for imaging a subject image. A light receiving surface is disposed at an image forming position of the objective optical system 15. The CCD 16 includes a CCD 16 as an image pickup unit for picking up the subject image formed at 15 and a waveform shaping circuit 17 for shaping a waveform of the input / output signal of the CCD 16. A signal line for transmitting a signal input / output to / from the CCD 16 via the waveform shaping circuit 17 is inserted through the endoscope 2 so that the connector 1
4 is electrically connected.

The video processor 3 includes the CCD 1
6 for driving a video signal or generating a video signal
SP21 (DSP is an abbreviation of a digital signal processor), a drive amplifier 22 for amplifying a drive signal output from the video signal processing DSP 21 and driving the CCD 16, and an image pickup signal transmitted from the CCD 16 And a preamplifier 2 for performing
A CDS circuit 24 for performing a CDS (correlated double sampling) process on the image pickup signal output from the CDS 3 to extract a video signal component; and converting the video signal obtained by the CDS circuit 24 into a digital signal to convert the video signal into a digital signal. An A / D conversion circuit 25 to be provided to the processing DSP 21, and the video signal processing DSP
A control microprocessor 26 for controlling each part of the video processor 3 and the video processor 3;
And a setting switch 28 such as a DIP switch capable of detecting a setting state by the control microprocessor 26.

The video signal processing DSP 21 has the C
A CCD drive circuit 31 for outputting a drive signal for driving the CD 16; and an SSG 32 (synchronous signal generation circuit) for synchronously generating a drive signal applied to the CCD drive circuit 31 and a signal such as a sample hold signal applied to the CDS circuit 24.
A delay circuit 33 for delaying a drive signal supplied from the SSG 32 to the CCD drive circuit 31 and a sample hold signal supplied to the CDS circuit 24, respectively;
A video signal processing circuit 34 for performing various video signal processing on the digital video signal obtained by the A / D conversion circuit 25; and a D / A conversion by digitally modulating the video signal output from the video signal processing circuit 34. It is configured to include a digital encoder that converts an analog video signal that can be displayed on a monitor. The various video signal processes include, for example, a white balance correction process, an outline emphasis process, a gamma correction and a knee process, a luminance / color signal separation process, and the like.

As shown in FIG. 2, the delay circuit 33
It comprises a plurality of buffers 41 connected in series for delaying signals, and a selection circuit 42 for selecting and outputting the output of each buffer 41 according to the control of the control microprocessor 26. . At this time, the plurality of buffers 41 may be configured by connecting, for example, 100 buffers 41 each having a delay time of 1 nanosecond. As a result, the delay circuit 33 controls the control microprocessor 2
According to the control of No. 6, the drive signal and the sample hold signal can each be delayed by an arbitrary time.

Next, the operation of this embodiment will be described. SS
The drive signal output from the G 32 is delayed by the delay circuit 33, and is transmitted to the CCD 1 via the CCD drive circuit 31, the drive amplifier 22, the signal cable 13, and the waveform shaping circuit 17.
Given to 6. At this time, the control microprocessor 2
6 sets the selection circuit 42 of the delay circuit 33 according to the value set by the setting switch 28, and the delay circuit 33 delays the drive signal by the value set by the setting switch 28.

An image pickup signal obtained by the CCD 16 driven by the drive signal is supplied to a waveform shaping circuit 17 and a signal cable 13.
Is supplied to the CDS circuit 24 via the preamplifier 23. Further, the sample hold signal output from the SSG 32 is delayed by the delay circuit 33, and the CDS circuit 2
Given to 4. At this time, the control microprocessor 2
6 sets the selection circuit 42 of the delay circuit 33 in accordance with the value set by the setting switch 28, and the delay circuit 33 delays the sample hold signal by the value set by the setting switch 28.

The video signal obtained by the CDS circuit 24 is A
Is converted into a digital video signal by the / D conversion circuit 25,
This digital video signal is subjected to various video signal processings by a video signal processing circuit 34, and the digital encoder 3
5, the video signal is converted into a video signal that can be displayed on a monitor and output.

As described above, by setting the delay time of the drive signal and the sample hold signal with the setting switch 28 in accordance with the length of the signal cable 13 and the insertion portion 11, etc., the signal is input to the CDS circuit 24. The phase of the imaging signal and the sample-and-hold signal is corrected, and the video processor 3
Can obtain a normal video signal.

As described above, according to the present embodiment, the provision of the delay circuit 33 allows the cable length to be corrected. In addition, since the delay circuit 33 is configured to be incorporated in the video signal processing DSP 21, an increase in the number of components for providing the delay circuit 33 can be reduced, and the endoscope apparatus 1 can be configured at low cost. Therefore, according to the present embodiment, according to the present invention, the effect that the cable length can be corrected with an inexpensive configuration can be obtained by reducing the number of components. In addition, the delay circuit 33 has a variable delay time under the control of the control microprocessor 26. Therefore, the video processor 3 can control the plurality of types of endoscopes 2 having different lengths such as the signal cable 13 and the insertion section 11. Correspondingly, cable length correction can be performed.

FIG. 3 relates to a modification of the first embodiment.
FIG. 2 is a block diagram illustrating an overall configuration of the endoscope apparatus. In addition,
In the present modification, the same reference numerals are given to portions configured in the same manner as in the first embodiment, and description thereof will be omitted.

As shown in FIG. 3, in this modified example, instead of providing the setting switch 28 of the first embodiment (see FIG. 1), an identification signal for identifying the type of the endoscope 2 is provided. Is provided in the endoscope 2 and the identification signal from the identification signal generation circuit 51 is supplied to the control microprocessor 26 via the signal cable 13. Has become. The identification signal generation circuit may be any circuit that can provide the identification information of the endoscope 2 to the control microprocessor 26, and may be, for example, a simple switch or a circuit using a pull-up / pull-down resistor.

The ROM 27 stores software for obtaining a signal delay amount given to the delay circuit 33 from the identification information.
Sets the delay circuit 33 in accordance with the identification information given from the identification signal generation circuit 51.

Next, the operation of this modification will be described. In this modification, only the points different from the first embodiment will be described. When the connector 14 at the end of the signal cable 13 of the endoscope 2 is connected to the video processor 3, an identification signal for identifying the type of the endoscope 2 is sent from the identification signal generation circuit 51 to the control microprocessor 26. Given. Then, the control microprocessor 26 automatically sets the delay time of the delay circuit 33 according to the given identification information.

According to this modification described above, the following effect can be obtained in addition to the effect described in the first embodiment. In this modification, the operability is improved because the delay time of the delay circuit 33 is automatically set.

The present invention is not limited to the above-described embodiment, but can be variously modified without departing from the gist of the invention. For example, the ROM 27 is not limited to the mask ROM, and may be another storage element that can store software. Further, for example, the information set by the setting switch 28 is not limited to the information indicating the delay time of the delay circuit 33, and may be the information indicating the cable length. At this time, the ROM 27 stores software for obtaining setting information for the delay circuit 33 from information indicating the cable length. Further, for example, the information set by the setting switch 28 is not limited to the information indicating the delay time of the delay circuit 33, and may be identification information for identifying the type of the endoscope 2. At this time, the ROM 27 stores software for obtaining setting information for the delay circuit 33 from the identification information. Further, for example, the information given by the identification signal generation circuit 51 to the video processor 3 is not limited to identification information for identifying the type of the endoscope 2 and may be information indicating a cable length, or given to the delay circuit 33. Information indicating the delay time may be used. Further, the endoscope 2 is not limited to an electronic endoscope provided with an imaging unit at the distal end of the insertion section, and may be an optical endoscope in which an optical image of a subject image is emitted from an eyepiece. At this time, the imaging means is provided on a camera head or the like detachably connected to the eyepiece. At this time, the identification signal generation circuit 5
A circuit having the same function as that of 1 may be provided in the camera head.

In recent years, CC as an image pickup means provided at the distal end of the insertion section of the endoscope for picking up an image of a subject has been used.
2. Description of the Related Art An endoscope apparatus including a D and a video processor that drives and controls the CCD and obtains a video signal that can be displayed on a monitor from an imaging signal obtained by the CCD is widely used. In such an endoscope device, generally, a video processor outputs a drive signal for driving a CCD, and a signal cable for transmitting these signals delays until an imaging signal obtained by the CCD is input to the video processor. Occurs. Then, after the video signal component is extracted from the imaging signal by the video processor, for example, when performing a color separation process for separating the luminance component and the color difference signal component of the video signal, the video processor includes the video signal component included in the video signal due to the delay due to the signal cable. In some cases, an incorrect color difference signal is extracted due to a shift in pixel timing, and a normal color is not reproduced in a video signal output from a video processor. For example, Japanese Patent Application Laid-Open No. 6-2
No. 69404 proposes means for preventing deterioration of color reproducibility caused by signal delay time caused by cable length.

However, for example, see Japanese Patent Application Laid-Open No. 6-2694.
In the prior art shown in Japanese Patent Application Laid-Open No. 04-2004, etc., in order to constitute a means for preventing deterioration of color reproducibility, a delay which delays a control signal when performing video signal processing and corrects a phase with respect to a delay of an imaging signal. There is a drawback that the number of parts is increased and the cost is increased by providing a line or providing a circuit for generating a special control signal when performing color separation processing. Therefore, an endoscope apparatus which can prevent the deterioration of color reproducibility at a low cost with a simple configuration will be described below with reference to FIGS.

As shown in FIG. 4, the endoscope device 101 comprises:
An endoscope 102 that is inserted into a body cavity or a duct to observe a subject image, and a light source that is detachably connected to the endoscope 102 and generates illumination light to be supplied to the endoscope 102. It is configured to have the device 103.

The endoscope 102 has an elongated insertion portion 111 inserted into a body cavity or a duct, and the like.
And an operation unit 112 for grasping and operating the endoscope 102, inserted through the insertion unit 111 and the operation unit 112, and inserts illumination light emitted from the light source device. Light guide 113 for guiding light to the tip of section 111
A light distribution optical system 114 provided at the distal end of the insertion portion 111 for distributing illumination light emitted from the light guide 113 toward a subject; and a light distribution optical system 114 provided at the distal end of the insert portion 111 to form a subject image. An objective optical system 115, a light receiving surface is disposed at an image forming position of the objective optical system 115 at the tip of the insertion section 111, and a CCD 116 as an image pickup means for picking up a subject image, and a vicinity of a rear end side of the CCD 116 And a waveform shaping circuit 117 for shaping a signal input / output to / from the CCD 116 and the CCD 1 via the waveform shaping circuit 117 provided in the operation unit 112.
A video processor 118 having a function of driving and controlling the video processor 16 to obtain a video signal that can be displayed on a monitor from an image signal obtained by the CCD 116;
8 is provided with a white balance adjustment switch 119 for giving the video processor 118 an adjustment value when white balance adjustment is performed on the video signal.

The video processor 118 includes the CC
A video signal processing circuit 121 that drives and controls the D 116 to obtain a video signal that can be displayed on a monitor from the imaging signal obtained by the CCD 116; a control microprocessor 122 that controls the video processor 118 such as the video signal processing circuit 121; A ROM 123 for storing software executed by the control microprocessor 122; and a gain referred to by the control microprocessor 122 when the control microprocessor 122 controls a gain of a video signal processed by the video signal processing circuit 121. It has a gain setting circuit 124 for setting information.

The video signal processing circuit 121 is provided with the CC
D116, a driving signal for driving the CCD 11 is generated.
6. A video signal processing DSP 131 having a function of inputting a digital video signal obtained by converting the imaging signal obtained in step 6 and obtaining a video signal that can be displayed on a monitor, and a drive output from the video signal processing DSP 131 A drive amplifier 132 for amplifying a signal and supplying a drive signal to the CCD 116 via the waveform shaping circuit 117; a preamplifier 133 for amplifying an imaging signal obtained from the CCD 116 via the waveform shaping circuit 117; 13
A CDS circuit 134 for performing a CDS (correlated double sampling) process on the image pickup signal output from the CDS 3 to extract a video signal component; and converting the video signal obtained by the CDS circuit 134 into a digital signal to convert the video signal into a digital signal. DSP 13 for processing
1 is provided with an A / D conversion circuit 135 to be given to the A / D converter 1.

The video signal processing DSP 131 is an SSG 141 (synchronous signal generation circuit) that synchronously generates a basic signal for generating a drive signal and a basic signal when each section of the video signal processing circuit 121 operates. And this S
The CCD drive TG 142 (TG is an abbreviation of a timing generator) that generates a drive signal in accordance with the basic signal provided from the SG 141, and operates in accordance with the synchronization signal provided from the SSG 141, and the A / D conversion circuit 13
5, a color separation circuit 143 for obtaining a luminance signal Y and color difference signals RY and BY from the digital video signal given from
The control microprocessor 1 according to the states of the gain setting circuit 124 and the white balance adjustment switch 119
22, a variable digital amplifier 144 for adjusting the white balance by amplifying each of the color difference signals RY and BY, and a luminance signal Y input from the color separation circuit 143 and the white balance adjustment signal. Y / C separated video, which is a video signal that can be displayed on a monitor, is subjected to digital modulation by applying digital modulation to a video signal composed of color difference signals RY and BY input from the variable digital amplifier 144 for white balance adjustment. It has a digital encoder 145 for obtaining a signal and a composite video signal.

The gain setting circuit 124 includes a metal halide lamp R gain setting trimmer 151a for setting a gain of a red component of a video signal when the metal light source lamp is mounted on the light source device 103; Apparatus 1
03, a xenon lamp R gain setting trimmer 151b for setting the gain of the red component of the video signal when the xenon lamp is mounted, and the video signal when the metal halide lamp is mounted on the light source device 103. A metal gain lamp B gain setting trimmer 151c for setting the gain of the blue component; and a xenon lamp B gain setting trimmer for setting the gain of the blue component of the video signal when the xenon lamp is mounted on the light source device 103. 151d,
Under the control of the control microprocessor 122, a gain setting signal according to the type of the lamp mounted on the light source device 103 is selected, that is, an R gain setting trimmer 151a for the metal halide lamp and a B for the metal halide lamp.
A selection circuit 152 for selecting and passing a gain setting signal from one of the combination of the gain setting trimmer 151c and the combination of the x gain setting R trimmer 151b for the xenon lamp and the x gain setting trimmer 151d for the xenon lamp; It has A / D conversion circuits 153a and 153b that convert the setting signals of the red component and the blue component that have passed through the circuit 152 into digital signals and provide the digital signals to the control microprocessor.

The light source device 103 emits illumination light, for example, a light source lamp 161 such as a metal halide lamp or a xenon lamp, and the illumination light emitted from the light source lamp 161 is collected and incident on the light guide 113. A converging optical system 162 to be operated, and an identification signal generating circuit 163 for supplying a signal indicating the type of the light source lamp 161 to the control microprocessor 122 of the video processor 118 are provided.

As shown in FIG. 5, the color separation circuit 143
A first line memory 1 controlled by a memory clock, a line memory address, a write signal, and a read signal, which are control signals supplied from the SSG 141, and sequentially storing digital video signals obtained by the A / D conversion circuit 135
71a, a second line memory 171b, a third line memory 171c, a fourth line memory 171d, and a subtractor 172a for subtracting signals read from the line memories 171a and 171b to obtain a color difference signal RY.
And a subtractor 172b for subtracting signals read from the line memories 171c and 171d to obtain a color difference signal BY, and passing a low frequency component of the digital video signal obtained by the A / D conversion circuit 135. And an LPF 173 (low-pass filter) for obtaining a luminance signal Y.

Next, of the operation of the endoscope apparatus 101 whose configuration has been described with reference to FIGS. 4 and 5, the operation relating to the entire operation will be described. Illumination light emitted from the light source lamp 161 of the light source device 103 is condensed by the condensing optical system 162, enters the light incident end of the light guide 113, is guided by the light guide 113, and is transmitted by the light distribution optical system 114. Irradiates the subject. At this time, the light source lamp 161
Can use different types of lamps, for example, any of a metal halide lamp and a xenon lamp. If the type of the light source lamp 161 is different, the subject is irradiated with illumination light having a different wavelength configuration.

An object image formed by the reflected light applied to the object is formed on the light receiving surface of the CCD 116 by the objective optical system 115. A drive signal output from the CCD drive TG 142 of the video signal processing circuit 121 is given to the CCD 116 via the drive amplifier 132 and the waveform shaping circuit 117, and the CCD 116 is driven by the drive signal and connected to the light receiving surface. An imaging signal corresponding to the formed subject image is output. The imaging signal is supplied to the CDS circuit 134 via the waveform shaping circuit 117 and the preamplifier 133. The CDS circuit 134 extracts a video signal component from the supplied imaging signal and supplies the video signal component to the A / D conversion circuit 135. This A
The / D conversion circuit 135 converts the video signal into a digital signal and supplies the digital signal to the color separation circuit 143. This color separation circuit 143
Converts a given video signal into a luminance signal Y and a chrominance signal R-
The luminance signal Y is converted into Y and BY, and is supplied to the digital encoder 145. Then, the color difference signals RY, BY
Is a variable digital amplifier 144 for white balance adjustment
, The respective levels are adjusted, and the resulting signals are supplied to the digital encoder 145. Digital encoder 14
5 is the given luminance signal Y, color difference signals RY, BY
Are digitally modulated and D / A converted to output a composite video signal and a Y / C separated video signal.

Next, the operation relating to the white balance adjustment will be described. Red and blue gain adjustment values when a metal haloid lamp is used as the light source lamp 161 are set in advance in the metal gain halo lamp R gain setting trimmer 151a and the metal haloid lamp B gain setting trimmer 151c. . Similarly, red and blue gain adjustment values when a xenon lamp is used as the light source lamp 161 are previously set in the xenon lamp R gain setting trimmer 151b and the xenon lamp B gain setting trimmer 151d.

When the light source device 103 is mounted on the endoscope 102, the identification signal generation circuit 16 of the light source device 103
3 provides an identification signal to the control microprocessor 122. The control microprocessor 122 selects the selection circuit 1 according to the type of the light source lamp 161 of the light source device 103.
52 is switched, either a combination of the metal gain lamp R gain setting trimmer 151a and the metal gain lamp B gain setting trimmer 151c or a combination of the xenon lamp R gain setting trimmer 151b and the xenon lamp B gain setting trimmer 151d. Pass the combination of signals. Then, the light source lamp 161
The red and blue gain setting values corresponding to the type are subjected to A / D conversion by A / D conversion circuits 153a and 153b, respectively.
It is provided to the control microprocessor 122. And
The control microprocessor 122 controls the given red and blue gain setting values and the white balance adjustment switch 119.
, The white balance adjustment variable digital amplifier 14 for each of the color difference signals RY and BY
4 and the white balance adjustment variable digital amplifier 144 corrects the levels of the color difference signals RY and BY.

Next, the operation relating to the color separation processing will be described. FIG. 6 shows an example of a pixel array of the CCD 116. In the figure, two fields forming a frame are referred to as an A field and a B field for convenience. “Cy” (cyan), “Ye” (yellow),
“G” (green) and “Mg” (magenta) mean the charge level or signal level of the color component of each pixel. As shown in the figure, one field line is composed of two pixel lines. For example, the n-th of the A field
The line is composed of a pixel line composed of Cy, Ye, Cy,... And a pixel line composed of G, Mg, G,. The horizontal transfer register provided in the CCD 116 for accumulating and transferring the signal for one field line stores the signal of the second line of the A field as G + C.
Signal values such as y, Mg + Ye, G + Cy,... are accumulated. The signal on the (n + 1) th line of the A field is
As described in the parentheses of the transfer register in the figure, Mg + Cy,
Signal values such as G + Ye, Mg + Cy,... Are accumulated. The signal stored in the horizontal transfer register is included in the imaging signal and transferred to the video signal processing circuit 121 on a field line basis, and is converted into a digital video signal.
The data is supplied to the color separation circuit 143 on a field line basis.

Each line memory 1 of the color separation circuit shown in FIG.
71a, 171b, 171c, and 171d have SSG1
From 41, a line memory address, a write signal, a read signal, and a memory clock are applied and controlled. At this time, the signal of the odd line of each field is supplied to the first line memory 171a and the second line memory 17a.
1b, and the signals of the even lines are controlled to be stored in the third line memory 171c and the fourth line memory 171d. Also, each pixel signal in each field line is associated with a line memory address in the order of 0, 1, 2, 3,..., And when the line memory address is an even number, the first line memory 171a and The third line memory 171c operates, and in the case of an odd number,
Line memory 171b and fourth line memory 171
d is controlled to operate.

As shown in FIG. 7, for example, when the n-th line of the A-field is an even-numbered line, the pixel signals of the n-th line of the A-field are G + Cy, Mg + Ye,
G + Cy,... Are input to the color separation circuit 143 in this order. Here, the line memory addresses of these pixel signals are
6, 7, 8,..., The first line memory 1
The G + Cy pixel signal is stored in 71a, and the Mg + Ye pixel signal is stored in the second line memory 171b. Similarly, in the case of pixel signals of odd lines, the third line memory 171c stores a pixel signal of Mg + Cy, and the fourth line memory 171d stores a pixel signal of G + Ye. Although the color configuration of the stored pixel signals is different for the B field, the pixel signals are stored by the same operation.

As for the pixel signals stored in the line memories 171a and 171b, pixel signals stored at the same address except for the least significant bit of the line memory address are read out at the same time and supplied to the subtractor 172a. The subtractor 172a outputs a pixel signal of a level obtained by subtracting the level of the pixel signal of the first line memory 171a from the level of the pixel signal of the second line memory 171b. As for the pixel signals stored in each of the line memories 171c and 171d, pixel signals stored at the same address except for the least significant bit of the line memory address are read out at the same time and supplied to the subtracter 172b. Vessel 1
72b outputs a pixel signal of a level obtained by subtracting the level of the pixel signal of the fourth line memory 171d from the level of the pixel signal of the third line memory 171c.

At this time, generally, the pixel signal and the color difference signal R
It is known that the relationship of -Y = (Mg + Ye)-(G + Cy) * BY = (Mg + Cy)-(G + Ye) * is -Y and BY. Therefore, as shown in FIG. 8A, the color difference signal RY is output from the subtractor 172a. In the figure, numerical values described as (6), (7), (8),... Indicate line memory addresses.
Similarly, the subtractor 172b outputs the color difference signal BY.

However, if the phase of the imaging signal input to the video signal processing circuit 121 is delayed by, for example, one pixel due to an electrical delay caused by a signal cable or the like, the phase of the video signal input to the color separation circuit 143 is reduced. Is delayed by one pixel. Then, as shown in FIG. 8B, the contents of the first line memory 171a and the second line memory 171b are reversed, and the color difference signal R is output from the subtractor 172a.
-Y cannot be obtained. Similarly, a subtractor 172
The color difference signal BY cannot be obtained from b.
The same applies to the case where the phase of the video signal is delayed by an odd number of pixels. Then, the color reproducibility of the video signal output from the digital encoder 145 deteriorates.

Therefore, the SSG 141 controls the operation of the color separation circuit 143 as described below. That is, SSG
141 controls the line memory address to be output to the color separation circuit 143 by delaying the line memory address start timing with respect to the reference timing such as the fall of the line reference signal indicating the transfer cycle of one line. At this time, the line memory address start delay time is
The setting is made according to the phase delay of the imaging signal. Thus, even if the phase of the video signal supplied to the color separation circuit 143 is delayed by an odd number of pixels, the correct color difference signals RY and BY are output from the color separation circuit 143 by adjusting the line memory address start timing. And digital encoder 1
The color reproducibility of the video signal output from the pixel 45 is maintained.

As described above, according to the endoscope apparatus 101, it is possible to prevent the color reproducibility of the output video signal from deteriorating.
Further, with a simple configuration in which the start timing of the line memory address given from the SSG 141 to the color separation circuit 143 is simply delayed, deterioration in color reproducibility can be prevented. Also, S
The SG 141 is configured in the video signal processing DSP 131, and performs various processes such as changing the contents of a storage element such as a ROM (not shown) that stores software executed by the video signal processing DSP 131. Since it is possible to prevent color reproducibility from deteriorating with respect to 102, it is possible to reduce additional components and cost. Therefore, the endoscope device 101
According to this, it is possible to prevent the deterioration of color reproducibility at a low cost with a simple configuration. Further, since the gain of each of the color difference signals RY and BY is automatically adjusted according to the type of the light source lamp 161, deterioration in color reproducibility due to using different types of light source lamps 161 is prevented. it can. In the example of the endoscope apparatus 101 shown in FIG. 4, the gain of the color difference signals RY and BY is set to the R gain setting trimmer 151 for the metal halide lamp.
a, the x gain setting trimmer 151b for the xenon lamp, the B gain setting trimmer 151c for the metal halide lamp, and the x gain setting trimmer 151d for the xenon lamp are set. The gain value is stored in the connected ROM 123, and the gain value can be selected and set by the control microprocessor 122. Further, a communication line with the outside (not shown) is provided in the control microprocessor 122, and a PC (personal computer) is connected through the communication line, and color difference signals RY, B are transmitted from the PC.
The gain of -Y may be set.

Although the video processor 118 is integrally formed with the endoscope 102 in the endoscope apparatus 101 whose configuration is shown in FIG. 4, the video processor is not limited to such a configuration. It may be configured separately from the mirror.

In recent years, endoscope apparatuses which can insert an elongated insertion portion into a body cavity or a duct to observe a subject in the body cavity or a duct have been widely used. The endoscope apparatus is configured, for example, as shown in FIG. An endoscope apparatus 301 shown in FIG. 15 includes an endoscope 302 that is inserted into a body cavity, a duct, or the like to obtain an imaging signal corresponding to a subject image, and a monitor that monitors the imaging signal obtained by the endoscope 302. Video processor 30 for obtaining a displayable video signal
3.

The endoscope 302 has an elongated insertion portion 311 to be inserted into a body cavity, a duct, or the like, and is provided continuously with a base end side of the insertion portion 311 to hold and operate the endoscope 302. , A signal cable 313 extending from the side of the operation unit 312 and transmitting a signal to and from the video processor 303, provided at an end of the signal cable 313, and detachably attached to the video processor 303. A connector 314 that is connected to the camera, an objective optical system 315 that is provided at the distal end of the insertion portion 311 and forms an object image, and an imaging unit that captures the object image formed by the objective optical system 315. It has a CCD 316.

The video processor 303 includes a control microprocessor 321 for controlling each part of the video processor 303, an operation switch 322 connected to the control microprocessor 321 for operating the video processor 303, and a video processor 303. Timing generator 3 for generating a control signal to be given to each unit
23, a function of controlling an electronic shutter function of the CCD 315, a CCD drive / shutter setting circuit 324 for generating a drive signal of the CCD 315, and an amplifying drive signal generated by the CCD drive / shutter setting circuit 324; A CCD drive circuit 325 applied to the CCD 316; and a CDS / AGC circuit 33 for performing a CDS (correlated double sampling) process and an AGC (automatic gain control) process on an image signal obtained by the CCD 316 to extract a video signal component.
1, an A / D conversion circuit 332 for converting the video signal obtained by the CDS / AGC circuit 331 into a digital signal,
A video signal correction circuit 333 that performs a correction process or the like on the video signal obtained by the A / D conversion circuit 332 to obtain a video signal composed of a luminance signal and a color signal;
33, a memory controller 335 for controlling the frame memory 334, and digitally modulating the video signal from the frame memory 334 before D / A conversion for monitor display. It has a digital encoder 336 that obtains a suitable video signal.

The video signal correction circuit 333 includes, for example,
OB (optical black) clamp circuit 314,
Gamma correction circuit 342, white clip circuit 343,
Including a filter circuit 344 and an enhancement circuit 345;
A luminance signal correction circuit 333a that performs correction processing or the like on the luminance signal component of the video signal, a color separation circuit 351, a color gamma correction circuit 352, a filter circuit 353, and an R / B amplifier 354 that independently amplifies the red and blue components. And a color signal correction circuit 333b for performing a correction process or the like on the color signal components.

However, in a conventional endoscope apparatus such as the endoscope apparatus 301, there are special modes such as a long exposure mode in which the exposure time is extended and a dynamic range expansion mode in which the dynamic range of the video signal is extended. In order to execute processing in the operation mode, conventionally, a circuit for generating a control signal and a circuit for performing arithmetic processing of a video signal are newly added, which has led to an increase in cost. Therefore, an endoscope apparatus that can operate by switching between special operation modes such as a long exposure mode and a dynamic range expansion mode while reducing the amount of hardware to be added will be described with reference to FIGS.

As shown in FIG. 10, an endoscope 201 includes an elongated insertion portion 202 inserted into a body cavity or a duct, and the like.
An operation section 203 provided continuously to the base end side of the insertion section 202 for gripping and operating the endoscope 201, for example, a light source device 211 provided on the operation section 203 for supplying illumination light, A light guide 212 that penetrates through the operation section 203 and the insertion section 202 and guides illumination light emitted from the light source device 211 to the tip of the insertion section 202.
A light distribution optical system 213 provided at the distal end of the insertion portion 202 for distributing illumination light emitted from the light guide 212 toward a subject; and a light distribution optical system 213 provided at the distal end of the insert portion 202 to form a subject image. An objective optical system 214, a CCD 215 serving as an image pickup means for picking up a subject image formed by the objective optical system 214, having a light receiving surface disposed at an image forming position of the objective optical system 214 at the distal end of the insertion section 202; ,
For example, the CCD 215 is provided on the operation unit 203.
Processor 2 which drives and controls the video signal to obtain a video signal which can be displayed on a monitor from the image signal obtained by the CCD 215.
16 are provided.

The video processor 216 has the CC
D215 to generate a drive signal for driving,
And a video signal processing DSP 221 for converting a digital video signal obtained from the imaging signal obtained in step 215 into a video signal that can be displayed on a monitor (DSP is an abbreviation of a digital signal processor), and an output from the video signal processing DSP 221. The timing of the drive signal is converted and the CCD 21
5, a CDS / AGC circuit 223 that performs a CDS (correlated double sampling) process and an AGC (automatic gain control) process on an image signal obtained by the CCD 215 to extract a video signal component.
And converts the video signal obtained by the CDS / AGC circuit 223 into a digital signal,
An A / D conversion circuit 224 to be provided to the DSP 21 and the digital video signal being processed by the video signal processing DSP 221 are temporarily stored, and designated arithmetic processing is performed, and the video signal is returned to the video signal processing DSP 221. Image memory circuit 2
25 while transmitting information between the video signal processing DSP 221 and the drive signal timing conversion circuit 222.
And the video processor 21 such as the image memory circuit 225
It has a control microprocessor 226 for controlling the six components.

The DSP 221 generates a drive signal for driving the CCD 215 and supplies the drive signal to the drive signal timing conversion circuit 222 (TG is an abbreviation of a timing generator). The A / D conversion circuit 224 A video signal correction circuit 232 that performs a correction process or the like on the obtained video signal and supplies the video signal to the image memory circuit 225; and a digital modulation that performs digital modulation on the video signal returned from the image memory circuit 225 to perform D / A conversion A digital encoder 233 for obtaining a video signal that can be displayed on a monitor;
A memory control circuit 234 for generating a memory control signal to be applied to the image memory circuit 225 is provided.

The image memory circuit 225 is provided with A for convenience.
Of a video signal composed of two fields called a field and a B field, a field memory 251 for sequentially storing an A field video signal and a field memory 252 for sequentially storing a B field video signal
And an arithmetic processing circuit 271 for performing arithmetic processing and the like on the video signal data read from the field memories 251 and 252 under the control of the control microprocessor 226, and temporarily storing the video signal output from the arithmetic processing circuit 271. The video signal processing DSP 2 stores and stores the video signal.
21 is provided.

The arithmetic processing circuit 271 has two multipliers 272 for multiplying each of the video signal data read from the field memories 251 and 252 by a coefficient given from the control microprocessor 226, and the two multipliers 272 It has an adder 273 for adding the output video signal data.

Next, the operation related to the normal operation of the endoscope 201 will be described. Illumination light emitted from the light source device 211 is guided by the light guide 212 and is distributed to the light distribution optical system 2.
13 illuminates the subject.

The optical image of the subject irradiated with the illumination light is formed on the light receiving surface of the CCD 215 by the objective optical system 214, and the CCD 215 captures the subject image. Drive signal T
The drive signal generated in G231 is normally not subjected to timing conversion in the drive signal timing conversion circuit 222, and is supplied to the CCD 215, and the CCD 215 driven by the drive signal converts the imaging signal into the CDS / AGC circuit 22.
Give to 3. The CDS / AGC circuit 223 extracts a video signal component from a given image pickup signal and supplies it to an A / D conversion circuit 224. The A / D conversion circuit 224 converts the given video signal into a digital signal. To the video signal processing DSP 221. This video signal processing DSP 22
In step 1, a given video signal is subjected to correction processing and the like by a video signal correction circuit 232, for example, “Y: U:
V = 4: 2: 2 "to the image memory circuit 225 as a digital video signal output. In the image memory circuit 225, the given video signal is stored in the field memory 251,
The digital image signal is temporarily stored in the image processing circuit 252 and returned to the image signal processing DSP 221 via the frame memory 274 without being processed by the arithmetic processing circuit 271. In the video signal processing DSP 221,
The returned video signal is converted into a video signal that can be displayed on a monitor by the digital encoder 233 and output. At this time, the field memory 251 stores the DS for video signal processing.
The operation mode of the drive signal timing conversion circuit 222 and the operation processing circuit is controlled by the control microprocessor 226, which is controlled by the memory control signal from the memory control circuit 234 of P221.

In the endoscope 201, the memory control circuit 234
Controls the field memories 251 and 252, and the control microprocessor 226 controls the operation modes of the drive signal timing conversion circuit 222 and the arithmetic processing circuit 271.
It is possible to operate in a long-time exposure mode described below, in which the exposure time of the CD 215 is made longer than usual, and a dynamic range expansion mode, described later, in which the dynamic range of a video signal obtained from an image signal obtained by the CCD 215 is expanded. It has become.

Next, the operation related to the operation in the long exposure mode will be described. Endoscope 2 configured as shown in FIG.
01 is equivalent to the functional configuration shown in FIG. 11 in the long exposure mode. That is, as shown in FIG. 11, the drive signal timing conversion circuit 222 converts the timing of the vertical transfer signal φV among the drive signals and does not convert the timing of the other drive signals. Functionally, the read pulse timing converter 281 converts the timing of the vertical transfer signal φV.
And the other drive signals are passed as they are. Further, in the image memory circuit 225, the processing by the arithmetic processing circuit 271 is not performed, so that the image memory circuit 225 functionally transmits the video signals from the field memories 251 and 252 without passing through the arithmetic processing circuit 271. It is configured to return to the video signal processing DSP via the frame memory 274 as it is. Note that FIG.
In FIG. 10, the same parts as those in FIG. 10 are denoted by the same reference numerals.

As shown in FIG. 12, the video signal processing DSP
The vertical transfer signal φV output from the CCD 221 is
5 is a vertical transfer pulse having a cycle of 1/60 second, for example, which gives a timing when the CCD 215 transfers a signal of one field line to a transfer register (not shown) built in the CCD 215. Normally, a read pulse that gives the timing at which the CCD 215 includes one field line signal in the image pickup signal and outputs the signal is superimposed.

Read pulse timing converter 281
Is a vertical transfer signal φV obtained by converting the vertical transfer signal φV so as to thin out read pulses included in the vertical transfer signal φV.
a is output. The read pulse normally occurs at a period of 1/60 second, but in the example shown in FIG.
Since the reading pulse is generated once during the generation, the reading pulse is generated once every 1/20 second. Therefore,
As the read pulse period becomes longer, the CCD
The exposure cycle of 215 becomes longer.

Then, normally 1/6 from the CCD 215
While the imaging signal is output at a cycle of 0 second, in the long exposure mode, the imaging signal CC is output at a cycle of 1/20 second, for example.
Dout is output. This imaging signal CCDout is
The video signal is converted into a video signal and supplied to the image memory circuit 225. In the image memory circuit 225, the supplied video signal is interpolated by the field memories 251 and 252 and the frame memory 274 controlled by the memory control circuit 234. Video signal processing DSP2
Return to 21.

Next, the operation related to the operation in the dynamic range expansion mode will be described. In the dynamic range expansion mode, the drive signal timing conversion circuit 222 converts the timing of the electronic shutter signal SUB for controlling the electronic shutter function of the CCD 215 among the drive signals, and does not convert the timing of other drive signals. Also, the image memory circuit 2
In 25, the arithmetic processing is performed by the arithmetic processing circuit 271.

As shown in FIG. 13, the exposure cycle is reduced to 1/6 by a vertical transfer signal φV having a cycle of 1/60 seconds, for example.
0 seconds. Normally, the generation period of the electronic shutter signal SUB within the exposure cycle is constant, but in the dynamic range expansion mode, the electronic shutter signal SUB
The generation period of “a” is controlled by the control microprocessor 226 so that it differs depending on the field. During the exposure period of the CCD 215 within the exposure cycle, the electronic shutter signal S
Since the period from when the generation of UBa ends to when it starts, the exposure period of the CCD 215 changes by controlling the generation period of the electronic shutter signal SUBa. During this exposure period, the photometric information of the video signal obtained by the photometric circuit provided in the video signal processing DSP 221 such as the video signal correction circuit 232 is supplied from the video signal processing DSP 221 to the control microprocessor 226. The control microprocessor 226 controls according to the information.

C given the electronic shutter signal SUBa
The CD 215 outputs the imaging signal CCDout at the next read timing after the exposure period corresponding to SUBa ends. Then, when the exposure period is short, the level of the video signal component of the imaging signal CCDout decreases. Conversely, when the exposure period is long, the level of the video signal component of the imaging signal CCDout increases. Here, when the level of the video signal component exceeds a predetermined level, the video signal component is saturated as shown in the figure.

As described above, for example, field signals having different signal levels alternately are stored in the field memories 251 and 25.
2 are stored alternately. And each field memory 2
The video signals read from 51 and 252 are multiplied by correction coefficients by separate multipliers 271 and level corrected, and the video signals output from these two multipliers 272 are added in level by adder 273. This is provided to the frame memory 274. At this time, the correction coefficient given from the control microprocessor 226 to the multiplier 272 is, as shown in FIG.
Is controlled so as to be a function with respect to the photometric level of the video signal photometrically measured at. This function is, for example, a function in which a correction coefficient function for a high-level component of a video signal and a correction coefficient for a low-level component are superimposed. And
As shown in FIG. 13, the video signal supplied from the adder 273 to the frame memory is a signal with a wide dynamic range in which a saturated portion of the video signal is corrected. The frame memory 274 interpolates the video signal output from the adder 273 and returns it to the video signal processing DSP 221.

According to the endoscope 201 described above with reference to FIGS. 10 to 14, the DSP 221 for processing video signals
Controls the field memories 251 and 252 and the like, and the control microprocessor 226 controls the image memory circuit 225 and the drive signal timing conversion circuit 222, so that the long exposure mode and the dynamic range can be achieved without changing hardware. A special operation mode operation such as an enlargement mode can be switched.

The endoscope apparatus 101 shown in FIG. 10 and FIG. 11 has the video processor 216 integrated with the endoscope 201. However, the video processor 216 is not limited to such a configuration. May be configured separately from the endoscope.

Conventionally, a CCD provided at the distal end of the insertion section as an image pickup means for picking up a subject image, and an operation section provided to drive and control the CCD so that monitor display is possible based on an image signal obtained by the CCD. Video processor to obtain a video signal, provided in the operation unit as needed,
2. Description of the Related Art An endoscope which is convenient to carry with an LCD (Liquid Crystal Display) as a display means for displaying the video signal is known. However, conventionally, an endoscope including such a video processor has not been provided with an additional function such as a function of superimposing a date, a time, and arbitrary characters on a video signal. Therefore, an endoscope having a video processor and an additional function such as a function of superimposing a date, a time, and an arbitrary character on a video signal will be described below with reference to FIGS. 16 and 17. I do.

The endoscope 501 shown in FIG. 16 has an elongated insertion portion 502 to be inserted into a body cavity or a duct, and is provided continuously at the base end side of the insertion portion 502 to hold the endoscope 501. An operation unit 503 for operating, an operation unit switch 504 provided on the operation unit 503, a remote controller 505 connected by a cable extending from the operation unit 503, An objective optical system 511 for forming a subject image;
02, a light receiving surface is arranged at an image forming position of the objective optical system 511 at the tip of the CCD 512, and is provided in the CCD 512 as an imaging unit for imaging a subject image formed by the objective optical system 511, for example, in the operation unit 503; A video processor 513 that drives and controls the CCD 512 and obtains a video signal that can be displayed on a monitor from an image signal obtained by the CCD 512.
And an LCD monitor 514 provided in, for example, the operation unit 503 and depicting a video signal obtained by the video processor 513 (LCD is an abbreviation for a liquid crystal display).
For example, a battery 515 detachably attached to the operation unit 503 to supply power to each unit of the endoscope 501 such as the video processor 513 and the LCD monitor 514, and a video camera detachably attached to the operation unit 503, for example. A battery such as a watch lithium battery 516 that supplies power for maintaining a clock function in the processor 513 is configured.

The video processor 513 includes an oscillator such as a system clock crystal oscillator 521 for oscillating a system clock supplied to each section of the video processor 513, and a C for generating a drive signal for driving the CCD 512.
A CD drive circuit 522 and a CDS (correlated double sampling) process and an AG
A CDS / AGC circuit 523 for performing a C (automatic gain control) process to extract a video signal component, an A / D conversion circuit 524 for converting a video signal obtained by the CDS / AGC circuit 523 into a digital signal, A video signal processing DSP 525 (DSP) for obtaining a composite video signal and a Y / C separated video signal, for example, analog video signals that can be displayed on a monitor from the digital signal obtained by the A / D conversion circuit 524.
Is an abbreviation of a digital signal processor), a synchronizing circuit 526 for synchronously generating a signal to be applied to each section of the video processor 513 such as the video signal processing DSP 525, and a video signal processing DSP 525 while transmitting information to the video signal processing DSP 525. A control microprocessor 527 for controlling each part of the processor 513; a ROM 528 for storing software executed by the control microprocessor 527; and a character generator 529 connected to the control microprocessor 527 for converting character data into pixel data.
Power is supplied from the watch lithium battery 516,
A clock IC 530 for providing date and time information to the control microprocessor 530, and the video signal processing DSP
A superimpose circuit 531 for superimposing the video signal in the process of 525 on the pixel data supplied from the control microprocessor 527 and returning the video signal to the video signal processing DSP 525, and a power supply line supplied from the battery 515. It has a power control circuit 532 that can be opened under the control of the control microprocessor 527.

As shown in FIG. 17, the video signal processing DSP 525 includes a luminance signal correction circuit 541a for performing a correction process or the like on the luminance signal component of the video signal obtained by the A / D conversion circuit 524, and a color signal component. A video signal correction circuit 541 for providing a video signal to the superimpose circuit 531 and a video signal returned from the superimpose circuit 531 after digitally modulating the video signal. A digital encoder 542 that performs D / A conversion to obtain a composite video signal and a Y / C separated video signal, and an SSG 543 (synchronization signal) that generates a control signal to be supplied to the superimpose circuit 531 in accordance with a synchronization signal supplied from the synchronization circuit 526 Generating circuit) and a serial interface for transmitting information to and from the control microprocessor 527. It is configured to include a over scan 544.

The superimpose circuit 531 is provided with, for example, 16
A latch circuit 551 for latching a video signal in a bit “Y: U: V = 4: 2: 2” format, and the latch circuit 551
A frame memory 552 for temporarily storing, for example, a 16-bit video signal output from the CPU, a video display processor 553 receiving a pixel signal or the like from the control microprocessor 527 and generating, for example, a 24-bit RGB video signal, Processor 55
3 is subjected to color difference conversion processing on, for example, a 24-bit RGB video signal, and for example, 16-bit “Y: U: V =
A color difference conversion circuit 554 for obtaining a video signal of 4: 2: 2 format
And a digital selector 555 controlled by the video display processor 553 to superimpose the video signal from the frame memory 552 and the video signal from the color difference conversion circuit 554 and return the video signal to the video signal processing DSP 525. It is configured.

Next, the operation of the endoscope 501 whose configuration has been described with reference to FIGS. 16 and 17 will be described. CCD 512 driven by a drive signal from CCD drive circuit 522
Supplies the imaging signal corresponding to the subject image to the CDS / AGC circuit 523, which extracts a video signal component from the supplied imaging signal and supplies the video signal component to the A / D conversion circuit 524. The / D conversion circuit 524 converts the supplied video signal into a digital signal and supplies the digital signal to the video signal processing DSP 525. This video signal processing DSP 5
At 25, a video signal correction circuit 54
1 performs correction processing and the like, for example, “Y: U: V = 4: 2:
The video signal of the "2" format is supplied to the superimpose circuit 531. In the superimpose circuit 531, a given video signal is synchronized by a latch circuit 551, temporarily stored in a frame memory 552, and stored in a digital selector 55.
5 given.

On the other hand, the control microprocessor 527
Date and time information is obtained from the clock IC 530. Then, the control microprocessor 527 supplies the character information indicating the date and time information to the character generator 529.
, And is given to the video display processor 553 of the superimpose circuit 531. At this time, the date and time of the clock IC 530 are corrected by an operation input from the operation unit switch 504 or the remote controller 505. Further, the control microprocessor 527 can obtain arbitrary character information from the operation unit switch 504 or the remote controller 505.
Then, the control microprocessor 527 converts the arbitrary character information into pixel information by the character generator 529 and provides the pixel information to the video display processor. Pixel information corresponding to characters indicating date and time and arbitrary characters are converted by the video display processor 553 into, for example, RGB format video signals, and the RGB format video signals are converted into, for example, “Y” by the color difference conversion circuit 554. :
The video signal is converted into a U: V = 4: 2: 2 "format video signal and supplied to the digital selector.

Then, the digital selector 555 converts the video signal from the frame memory 552 into a color difference conversion circuit 55.
4 is superimposed, for example, “Y: U: V = 4:
A video signal processing DSP 525 for converting a 2: 2 "format video signal.
Return to The superimposed video signal is converted by a digital encoder 542 of the DSP 525 into, for example, a composite video signal that can be displayed on a monitor and output. The composite video signal is supplied to an LCD monitor 514, and an image in which characters indicating the date and time and arbitrary characters are superimposed on the subject image is displayed on the LCD monitor 514.

Further, the control microprocessor 527 includes:
When the time given from the clock IC 530 reaches a predetermined time, the power supply control circuit 532 is controlled, whereby the power supplied from the battery 515 to each part of the endoscope 501 is cut off.

According to the endoscope 501 described above with reference to FIGS. 16 and 17, the superimpose circuit 531
By providing the control microprocessor 527, the clock IC 530, the operation unit switch 504, and the character generator 529 in the endoscope 501, the display of the date and time and the display of arbitrary characters can be performed on the subject image without providing an external device. They can be superimposed and displayed. In addition, D for video signal processing
The video signal including the date, time, and any characters is superimposed on the video signal being processed by the SP 525, and the superimposed video signal is returned to the DSP 525 for video signal processing. It is not necessary to newly provide a circuit such as a processor for converting into a signal, so that the number of parts can be reduced and the configuration can be made inexpensively. Watch I
C530, and a control microprocessor 527
Is provided, the power supply control circuit 532 that can cut off the power supplied from the battery 515 can be controlled to automatically turn off the power at a predetermined time.

Further, since the clock lithium battery 516, which is a power supply for the clock IC 530, is provided, the clock IC 530 always updates the time even when the power supplied from the battery 515 to each part of the endoscope 501 is cut off. can do.

[Supplementary Note] (Supplementary note 1-1) A means for generating a first drive signal for driving an image pickup means built in or detachably connected to the endoscope, and a signal obtained by the image pickup means. A video signal extracting unit that obtains a first video signal included in an imaging signal; and a timing when the video signal extracting unit drives the video signal extracting unit to obtain the first video signal from the imaging signal. And a first processor storing at least a part of a circuit for obtaining a monitor-displayable second video signal from the first video signal. An endoscope apparatus comprising: a delay circuit for delaying at least a part of signals included in the first drive signal and the second drive signal stored in the first processor. .

(Additional Item 1-2) The endoscope apparatus according to additional item 1-1, wherein the first processor is a digital signal processor formed of an integrated circuit.

(Additional Item 1-3) In the endoscope apparatus according to Additional Item 1-1, the delay circuit has a variable delay time.

(Additional Item 1-4) In the endoscope apparatus according to additional item 1-3, the delay circuit includes a multi-stage buffer circuit connected in series and a multi-stage buffer circuit. Circuit to select.

(Additional Item 1-5) The endoscope apparatus according to Additional Item 1-3, further comprising a second processor for setting a delay time of the delay circuit.

(Additional Item 1-6) The endoscope apparatus according to Additional Item 1-5, further comprising a switch for designating the delay time, wherein the second processor sets the state of the switch. The delay time is set accordingly.

(Additional Item 1-7) The endoscope apparatus according to Additional Item 1-5, further comprising: a switch for setting information from which the delay time can be derived, wherein the second processor includes: The delay time is set according to the state of the switch.

(Additional Item 1-8) In the endoscope apparatus according to Additional Item 1-7, the information from which the delay time can be derived includes:
The information includes information indicating the length of the insertion section of the endoscope.

(Additional Item 1-9) In the endoscope apparatus according to Additional Item 1-7, the information from which the delay time can be derived includes:
It includes identification information for identifying the type of the endoscope.

(Additional Item 1-10) The endoscope apparatus according to Additional Item 1-5, wherein the endoscope includes information notifying means for providing information indicating the delay time to the second processor. And the second processor sets the delay time according to information notified from the information notifying unit.

(Additional Item 1-11) The endoscope apparatus according to Additional Item 1-5, wherein the endoscope provides the second processor with information capable of deriving the delay time. Means, and the second processor sets the delay time according to information notified from the information notification means.

(Additional Item 1-12) In the endoscope apparatus according to Additional Item 1-11, the information from which the delay time can be derived includes information indicating a length of an insertion portion of the endoscope. Including.

(Additional Item 1-13) In the endoscope apparatus according to Additional Item 1-11, the information from which the delay time can be derived includes identification information for identifying the type of the endoscope. Including.

(Additional item 2-1) Imaging means for imaging a subject image, means for obtaining a digital video signal from the imaging signal obtained by the imaging means, and obtaining an analog video signal which can be displayed on a monitor from the digital video signal In an endoscope apparatus having a first processor storing at least a part of a video signal processing circuit, a plurality of line memories for holding one horizontal period signal and a timing of taking data into the line memories are delayed. Line memory control means that can be used by switching between a case where the image is captured without a signal and a case where the image is captured with a predetermined time delay. When the pixel is delayed by an odd number of pixels based on the scanning period, the line memory is delayed by a predetermined time by the line memory control means. An electronic endoscope apparatus which is characterized in that takes in the signal processing a digital video signal from the imaging means to the directory. (Additional Item 2-2) In the endoscope apparatus according to Additional Item 2-1, the setting of the line memory control unit is set by a second processor provided outside the first processor.

(Additional Item 2-3) The endoscope apparatus according to additional item 2-1 wherein the setting of the line memory control means is performed by a second processor provided outside the first processor and a second processor provided outside the first processor. The setting is made by an identification signal indicating the insertion section length of the endoscope which is input to the second processor.

(Appendix 3-1) Imaging means for imaging the subject image, drive signal generation means for generating a drive signal for driving the subject image, and a video signal from the imaging signal obtained by the imaging means , A first processor storing main control means for controlling each unit, a second processor storing at least a part of a circuit for performing video signal processing on the video signal, and the first processor. An operation mode control means for controlling an operation mode of the imaging means stored in the storage means, and a drive signal timing change means capable of changing a timing of a drive signal given to the imaging means according to control from the operation mode control means, A memory for temporarily storing at least a video signal during the video signal processing; and a memory stored in the second processor, Depending on your endoscope apparatus which is characterized in that a memory control signal generating means for generating a control signal for controlling the operation of the memory.

(Additional Item 3-2) In the endoscope apparatus according to Additional Item 3-1, the drive signal timing changing means may generate a shutter drive signal for driving an electronic shutter function of the imaging means. Can be changed.

(Additional Item 3-3) In the endoscope apparatus according to Additional Item 3-1, the memory may store each frame included in the video signal under the control of the first control means. Means for performing arithmetic processing on the signal of

(Additional Item 3-3) In the endoscope apparatus according to Additional Item 3-1, the memory may store each frame included in the video signal under the control of the first control means. Means for synthesizing the signals.

[0100]

As described above, according to the present invention,
By reducing the number of parts, the effect that the cable length can be corrected with an inexpensive configuration can be obtained.

[Brief description of the drawings]

FIG. 1 and FIG. 2 relate to a first embodiment of the present invention, and FIG. 1 is a block diagram showing an entire configuration of an endoscope apparatus.

FIG. 2 is a block diagram illustrating a configuration of a delay circuit.

FIG. 3 is a block diagram showing an overall configuration of an endoscope apparatus according to a modification of the first embodiment;

FIGS. 4 to 9 are referred to for description of an endoscope apparatus for correcting color misregistration with a simple configuration, and FIG. 4 is a block diagram showing an overall configuration of the endoscope apparatus.

FIG. 5 is a block diagram illustrating a configuration of a color separation circuit.

FIG. 6 is an explanatory diagram showing correspondence between colors of CCD pixels and fields.

FIG. 7 is a time chart showing data storage timing of a line memory;

8A and 8B are explanatory diagrams showing a relationship between data content of a line memory and an output of a subtractor, wherein FIG. 8A is an explanatory diagram showing an operation when there is no cable delay, and FIG. Explanatory diagram showing the operation in the event of occurrence of

FIG. 9 is an explanatory diagram showing a line memory address start timing.

10 to FIG. 14 are referred to for description of an endoscope in which a special effect function is added to a video signal processing function with an inexpensive configuration, and FIG. 10 is a block diagram showing an overall configuration;

FIG. 11 is a block diagram showing a functional configuration of an endoscope in which functions related to a long-time exposure function are extracted.

FIG. 12 is a time chart illustrating an operation of a long-time exposure function;

FIG. 13 is a time chart showing the operation of the dynamic range expansion function.

FIG. 14 is an explanatory diagram illustrating an example of characteristics of a correction coefficient used in a dynamic range expansion function.

FIG. 15 is a block diagram showing a configuration of an endoscope apparatus used for explaining a conventional technique of an endoscope described with reference to FIGS. 10 to 14;

16 and 17 refer to the description of an endoscope having an additional function such as a function of superimposing a date, a time, and an arbitrary character on a video signal, and FIG. 16 illustrates an entire configuration of the endoscope. Block Diagram

FIG. 17 shows a superimpose circuit and a video signal processing D.
Block diagram showing detailed configuration of SP

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Endoscope apparatus 2 ... Endoscope 3 ... Video processor 11 ... Insertion part 13 ... Signal cable 16 ... CCD 21 ... Video signal processing DSP 24 ... CDS circuit 25 ... A / D conversion circuit 26 ... Control microprocessor 27 ... ROM 28 ... Setting switch 31 ... CCD drive circuit 32 ... SSG 33 ... Delay circuit 34 ... Video signal processing circuit 35 ... Digital encoder 51 ... Identification signal generation circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H040 BA00 GA01 GA02 GA11 4C061 AA00 BB02 CC06 DD00 FF45 JJ19 LL02 LL03 MM05 NN03 NN05 PP19 SS03 SS11 SS30 TT12 UU03 UU09 5C054 AA01 CC07 EB02 HA12

Claims (1)

[Claims] 1. A means for generating a first drive signal for driving an image pickup means built in or detachably connected to an endoscope, and a first drive signal included in the image pickup signal obtained by the image pickup means A video signal extracting unit that obtains a video signal; and a second drive signal that drives the video signal extracting unit and controls a timing when the video signal extracting unit obtains the first video signal from the imaging signal. And a first processor storing at least a part of a circuit for obtaining a second video signal that can be displayed on the monitor from the first video signal, wherein the first processor stores the first video signal. An endoscope apparatus comprising a delay circuit for delaying at least a part of signals included in the first drive signal and the second drive signal.