JP2007067340A - Semiconductor integrated circuit device and method for testing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To find out a fuse element which is cut halfway. <P>SOLUTION: A control signal CNT is turned into a high level and an NMOS transistor Q0 is turned on. Since a resistance value of a resistor R0 is a predetermined value at manufacturing a semiconductor integrated circuit device beforehand, a current I0 flowing through a measuring terminal P0 is measured by an external tester or the like, thereby determining a resistance value of a fuse element F0. If the resistance value (r) of the fuse element F0 is a certain value r1 or larger, for example, it is determined that the fuse element F0 is cut. If the resistance value (r) is a certain value r2 or smaller, it is determined that the fuse element is not cut. In the case of r2<r<r1, it is determined that the fuse element is cut incompletely. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device and a test method thereof, and more particularly to a semiconductor integrated circuit device including a trimming element such as a fuse and a test method thereof.

  The trimming detection circuit, in which the output of the bit logic is fixed to a high (H) level or a low (L) level by an electrically disconnectable trimming element, functions of electronic circuits, setting of operation parameters, reference voltage Widely incorporated in semiconductor devices (IC chips) for the purpose of fine adjustment of the output voltage of the generation circuit. As a trimming element mounted on a semiconductor device, a laser fuse that burns out wiring with a laser, a zener zap that burns out a Zener diode, a so-called E fuse that is electrically cut by Joule heat generated when a current is passed through the trimming element, and the like. Are known.

  It is known that a disconnection failure may occur in the fuse cutting of such a trimming detection circuit. For example, in the case of cutting with a laser, a part of the dissolved residue may be attached in the vicinity of the element and may be connected with a halfway resistance value without being completely cut. For this reason, when a fuse to be cut is cut halfway or when a fuse that should not be cut is cut accidentally and cut halfway, the fuse can be reliably removed as a defective product. Such a semiconductor device is disclosed in Patent Document 1.

  FIG. 8 is a circuit diagram of the semiconductor device described in Patent Document 1. In FIG. In FIG. 8, the semiconductor device has a fuse 101 and a resistor 102 connected in series between the power supply potential VDD and the ground, and an input terminal connected to a connection point between the fuse 101 and the resistor 102, and determines whether the fuse 101 is cut or not. A determination circuit 103, a test resistor 108, and a transistor 107 that connects the test resistor 108 in parallel with the fuse 101 during testing and does not connect the test resistor 108 during normal operation. In the semiconductor device configured as described above, the transistor 107 is turned off during normal use and the test resistor 108 is not connected to the fuse 101, and the test resistor 108 is connected in parallel to the fuse 101 while the transistor 107 is turned on during a shipping test. . By operating the transistor 107 in this way, it should have been cut, but it was shipped as a non-defective product while being cut halfway, but shipped a defective fuse that was judged as a defective product during normal use by the customer Can be eliminated during testing.

Japanese Patent Laid-Open No. 10-62477 (FIG. 1)

  By the way, in the semiconductor device described in Patent Document 1, it is determined whether the cutting is halfway or complete, depending on whether the voltage at the input terminal of the determination circuit 103 is larger or smaller than the threshold value. However, the fuse that is cut halfway (half-cut) may malfunction due to fluctuations in its resistance value or re-adhesion depending on the usage environment (power supply voltage, temperature, etc.) and changes over time. It may cause For this reason, it is necessary to detect a “half-cut state” existing in a wider range of resistance values. However, in the conventional detection method based on logical GO / NOGO determination (0, 1 determination) based simply on a threshold value. Therefore, it was difficult to detect a “half-cut state” existing in a wide resistance value range.

  A semiconductor integrated circuit device according to one aspect of the present invention includes a cascade connection circuit of a fuse element and a first switch element, an energization element, one end of the cascade connection circuit, and one end of the energization element connected to an input end. And one or more trimming detection circuits including a determination circuit for determining whether the fuse element is intermittent. In addition, the measurement is interposed between the other end of each energization element connected in common and the first power supply, or between the other end of each cascade connection circuit connected in common and the second power supply. Provide terminals.

  A test method for a semiconductor integrated circuit device according to one aspect of the present invention includes a cascade connection circuit of a fuse element and a first switch element, an energization element, one end of the cascade connection circuit, and one end of the energization element. 1 or 2 or more trimming detection circuits including a determination circuit that determines whether the fuse element is intermittent, and between the other end of each energization element connected in common and the first power source, or This is a test method for a semiconductor integrated circuit device including a measurement terminal interposed between the other end of each cascade connection circuit connected in common and a second power supply. In this method, only the first switch element in the trimming detection circuit including the fuse element to be tested is short-circuited, and the current at the measurement terminal is measured.

  According to the present invention, by measuring the resistance value of a fuse element, it is possible to find a fuse element that is cut halfway with a wider range of resistance values.

  FIG. 1 is a circuit diagram of a trimming detection circuit portion of a semiconductor integrated circuit device according to an embodiment of the present invention. In FIG. 1, the trimming detection circuit includes a fuse element F0, an NMOS transistor Q0, an inverter circuit INV, a resistor R0, and a measurement terminal P0. The source of the NMOS transistor Q0 is grounded, the gate is supplied with the control signal CNT, and the drain is connected to one end of the fuse element F0. The other end of the fuse element F0 and one end of the resistor R0 are connected to the input end of the inverter circuit INV. The other end of the resistor R0 is connected to the power supply VDD via the measurement terminal P0. The resistor R0 may be formed of a semiconductor element that supplies current to the fuse element F0.

  The trimming detection circuit configured as described above turns on the NMOS transistor Q0 by setting the control signal CNT to the high level during the normal operation of the semiconductor integrated circuit device including the trimming detection circuit. If the fuse element F0 is cut in this state, the input terminal of the inverter circuit INV becomes the potential of the power supply VDD, and the output signal VOUT of the inverter circuit INV becomes low level. If the fuse element F0 is not cut, the input terminal of the inverter circuit INV becomes a ground potential, and the output signal VOUT of the inverter circuit INV becomes high level. That is, the cut state of the fuse element F0 appears as the signal level of the output signal VOUT.

  On the other hand, also when testing the semiconductor integrated circuit device, that is, when testing the cutting state of the fuse element F0, the control signal CNT is set to the high level to turn on the NMOS transistor Q0. Since it is known that the resistance value of the resistor R0 is a predetermined value at the time of manufacturing the semiconductor integrated circuit device in advance, the current I0 flowing through the measurement terminal P0 is measured by an external tester or the like, so that the fuse element F0 The resistance value can be obtained. For example, the fuse element F0 is determined to be disconnected if the resistance value r of the fuse element F0 is equal to or greater than a certain value r1, and is not disconnected if the resistance value r is equal to or less than a certain value r2. If r2 <r <r1, it is considered that it has been cut incompletely (half cut state). Thus, by determining the resistance value itself of the fuse element, it is possible to accurately grasp the incompletely cut fuse element. Since the measurement terminal P0 only needs to be able to measure the current flowing through the fuse element, the measurement terminal P0 may be provided on the ground side instead of the power supply VDD side.

  By testing the semiconductor integrated circuit device as described above, it is determined that the fuse element has become a high resistance and has been cut, and the resistance value decreases over time so that the output signal VOUT differs from the predetermined setting. It is possible to detect the change at an early stage. Hereinafter, a detailed description will be given in accordance with examples.

  FIG. 2 is a circuit diagram of a trimming detection circuit portion of the semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG. 2, the trimming detection circuit includes n trimming detection circuits (n is a natural number) shown in FIG. The fuse elements F1 to Fn are equivalent to the fuse element F0, the NMOS transistors Q1 to Qn are equivalent to the NMOS transistor Q0, the inverter circuits INV1 to INVn are equivalent to the inverter circuit INV, and the resistors R1 to Rn are equivalent to the resistor R0.

  The other ends of the resistors R1 to Rn are common to all the trimming detection circuits, and are connected to the power supply VDD via the measurement terminal P0. The measurement terminal P0 is preferably one that can detect a current flowing through the fuse elements F1 to Fn by connecting a tester such as a pad connected outside the chip or a pad arranged inside the chip. The measurement terminal P0 is preferably connected to a tester in the resistance measurement of the fuse element, and is preferably connected to the power supply VDD by performing wiring such as bonding for normal operation before shipment after the measurement is completed.

  The trimming detection circuit configured as described above turns on the NMOS transistors Q1 to Qn by setting all the control signals CNT1 to CNTn to the high level during the normal operation of the semiconductor integrated circuit device including the trimming detection circuit. If the fuse element Fi (i = 1 to n) is cut in this state, the input terminal of the inverter circuit INVi becomes the potential of the power supply VDD, and the output signal VOUTi of the inverter circuit INVi becomes a low level. If the fuse element Fi is not cut, the input terminal of the inverter circuit INVi becomes a ground potential, and the output signal VOUTi of the inverter circuit INVi becomes high level. That is, the cutting information of the fuse element Fi appears as the output signal VOUTi.

  Next, a test method at the time of fuse cutting will be described. FIG. 3 is a flowchart of the fuse measuring method according to the first embodiment of the present invention. In the fuse measurement method, for example, the fuse elements F1, F2,... Fn in FIG.

  In step S11, the fuse element Fi is cut.

  In step S12, the resistance value of the fuse element Fi after cutting is measured. Therefore, the control signal CNTi is set to the high level to turn on the NMOS transistor Qi. Note that the control signals CNTj (j ≠ i) other than the control signal CNTi are at a low level, and all the NMOS transistors Qj (j ≠ i) are turned off. The resistance value of the fuse element Fi is obtained by measuring the current I0 flowing through the measurement terminal P0 with an external tester or the like. Details of the resistance value measurement will be described later.

  In step S13, the fuse element Fi is determined to be disconnected if the resistance value r of the fuse element Fi is equal to or greater than a certain value r1, and is not disconnected if the resistance value r is equal to or less than a certain value r2. If r2 <r <r1, it is considered that it has been cut incompletely.

  In step S14, it is determined whether or not the resistance value measurement has been completed for all the fuse elements to be cut, and if not, the process returns to step S11 to cut the next fuse element to be cut.

  In the above method, the example in which the cutting of the fuse element and the measurement of the resistance value of the fuse element are repeated one by one is shown. However, all necessary fuse elements are cut in advance, and the fuse elements are sequentially The resistance value may be measured.

Next, the measurement of the resistance value will be described. FIG. 4 is a diagram schematically showing connection of resistors related to the fuse element measurement. In FIG. 4, the applied voltage of the power source VDD is VF, and the current measured by the ammeter A in the tester is IM. When the resistance value of the measurement path is R, the resistance value of the fuse element is Rfuse, the on-resistance of the NMOS transistor Qi is Rmn1, and the resistance value of the resistor R0 is Rr, the resistance value R of the measurement path is expressed by Equation (1). The
R = VF / IM = Rr + Rfuse + Rmn1 ---- Formula (1)

Here, since Rmn1 is extremely smaller than Rr, Rfuse can be obtained by Expression (2).
Rfuse = VF / IM-Rr ---- Formula (2)

  In the above description, the fuse element to be cut is determined in advance by the function setting of the semiconductor integrated circuit device. Alternatively, the fuse element may be cut while finely adjusting a predetermined operation of the semiconductor integrated circuit device. In this case, it is possible to cut the necessary fuse elements one after another so as to realize a predetermined function while confirming that the fuse elements are surely cut.

  As described above, the semiconductor integrated circuit device according to the present embodiment can directly measure the resistance value of the fuse element by measuring the resistance value of the measurement path. The element can be detected.

  Further, by turning on / off the NMOS transistor Qi by the control signal CNTi, the output signal VOUTi can be set without cutting the fuse element. Therefore, it is effective for testing and debugging the semiconductor integrated circuit device before the fuse is cut.

  Furthermore, when there are a plurality of fuse elements, the fuse element to be measured for resistance value can be arbitrarily selected and tested by the control signal CNTi, so that the test efficiency and test quality are high. In other words, the defect detection rate is high.

  Further, by performing both measurement of the resistance value of the fuse element and observation of the output signal VOUTi, it is possible to determine whether the fuse element is defective or the inverter circuit is defective when it is determined as defective. For example, despite the fact that the resistance value of the fuse element is a value indicating a disconnected state, even when the output signal VOUTi is at a high level, or the resistance value of the fuse element is a value indicating a connected state, When the output signal VOUTi is at a low level, a failure of the inverter circuit connected to the fuse element is assumed.

  FIG. 5 is a flowchart of a fuse measuring method according to the second embodiment of the present invention. The fuse measurement method according to the second embodiment is applied to the trimming detection circuit portion of the semiconductor device shown in FIG. 2, but in contrast to the measurement method of the first embodiment, the resistance value before the fuse element is cut. The point to measure is different.

  In step S21, the resistance value of the fuse element Fi (i = 1 to n) before cutting is measured. The control signal CNTi is set to high level to turn on the NMOS transistor Qi. Note that the control signals CNTj (j ≠ i) other than the control signal CNTi are set to a low level to turn off all the NMOS transistors Qj (j ≠ i). By measuring the current I0 flowing through the measurement terminal P0 with an external tester or the like, the resistance value of the fuse element Fi is obtained and held.

  Steps S22 and S23 are processed in the same manner as steps S11 and S12, respectively.

  In step S24, a difference between resistance values before and after the fuse element Fi is cut is obtained. As will be described below, the obtained difference is used to determine whether the resistance value after cutting is completely cut or incomplete.

  In step S25, processing similar to that in step S14 is performed.

Next, resistance values before and after the fuse element Fi is cut will be described. FIG. 6 is a diagram schematically illustrating connection of resistors according to the fuse element measurement before and after the fuse element is cut. FIG. 6A is a view before cutting, and FIG. 6B is a view after cutting. In FIG. 6, the applied voltage of the power supply VDD is VF, and the current measured by the ammeter A in the tester is IMuncut (FIG. 6 (a)) or IMcut (FIG. 6 (b)). Also, the resistance value of the measurement path before cutting is Runcut, the resistance value of the fuse before cutting is Rfuse, the resistance value of the measuring path after cutting is Rcut, the resistance value of the fuse after cutting is Rcutfuse, and the resistance value of the resistor R0 is When the on-resistance of Rr and NMOS transistor Qi is Rmn1, the difference ΔR between the resistance values before and after the fuse element Fi is cut is expressed by the following equation (3).
ΔR = Rcut−Runcut
= (Rr + Rcutfuse + Rmn1)-(Rr + Rfuse + Rmn1)
= Rcutfuse-Rfuse ---- Formula (3)

In Expression (3), Rcutfuse is extremely larger than Rfuse, and therefore Expression (3) is approximately expressed as Expression (4) below. That is, the difference ΔR between the resistance values before and after cutting becomes substantially equal to the resistance value of the fuse element after cutting.
ΔR = Rcutfuse ---- Formula (4)

Furthermore, the resistance value Rcut of the measurement path after the fuse is cut and the difference ΔR = Rcutfuse between the resistance values are classified as follows (a) to (c).
(A) When cut normally: Rcut = Rcutfuse = R∞ (high impedance)
(B) When not cut: Rcut = Runcut, Rcutfuse = Rfuse (resistance before cutting)
(C) When half cut: Runcut <Rcut <R∞, Rfuse <Rcutfuse <R∞

  From the above, it is possible to detect the half-cut more reliably by setting the determination condition in the case of the half-cut to a value close to the resistance value R∞ at the time of normal cutting.

  FIG. 7 is a circuit diagram of the trimming detection circuit portion of the semiconductor integrated circuit device according to the third embodiment of the present invention. In FIG. 7, the same reference numerals as those in FIG. The trimming detection circuit shown in FIG. 7 further includes an NMOS transistor Qa and a resistor Ra in addition to the trimming detection circuit of FIG. The source of the NMOS transistor Qa is grounded via the resistor Ra, the drain is connected to the input terminal of the inverter circuit INV, and the gate is supplied with the control signal CNTa.

  The semiconductor integrated circuit device having the above configuration has the same configuration as that of FIG. 1 when the NMOS transistor Qa is turned off. Therefore, during normal operation, the control signal CNT is set to the high level to turn on the NMOS transistor Q0, and the control signal CNTa is set to the low level to turn off the NMOS transistor Qa.

  On the other hand, in the test mode, the control signal CNTa is set to low level to turn off the NMOS transistor Qa, and the control signal CNT is set to high level to turn on the NMOS transistor Q0. Then, as described with reference to FIG. 1, the resistance value of the fuse element F0 is obtained by measuring the current flowing through the measurement terminal P0 with an external tester or the like. to decide.

  Alternatively, the control signal CNTa is set to high level to turn on the NMOS transistor Qa, and the control signal CNT is set to high level to turn on the NMOS transistor Q0. As described in the related art, the disconnection failure of the fuse element F0 may be determined by detecting that the output signal VOUT is at a high level even though the fuse element F0 is disconnected.

  The present invention has been described with reference to the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and those skilled in the art within the scope of the invention of each claim of the present application claims. It goes without saying that various modifications and corrections that can be made are included.

It is a circuit diagram of a trimming detection circuit portion of a semiconductor integrated circuit device according to an embodiment of the present invention. 1 is a circuit diagram of a trimming detection circuit portion of a semiconductor integrated circuit device according to a first embodiment of the present invention; FIG. It is a flowchart of the measuring method of the fuse which concerns on 1st Example of this invention. It is a figure which shows typically the connection of the resistor concerning a fuse element measurement. It is a flowchart of the measuring method of the fuse which concerns on the 2nd Example of this invention. It is a figure which shows typically the connection of the resistor which concerns on the fuse element measurement before and behind the cutting | disconnection of a fuse element. FIG. 7 is a circuit diagram of a trimming detection circuit portion of a semiconductor integrated circuit device according to a third embodiment of the present invention. It is a circuit diagram of the conventional semiconductor device.

Explanation of symbols

F0, F1-Fn Fuse elements Q0, Q1-Qn, Qa NMOS transistors INV, INV1-INVn Inverter circuits R0, R1-Rn, Ra resistance P0 Measuring terminals CNT, CNT1-CNTn, CNTa Control signal VDD Power supply

Claims (8)

A cascade connection circuit of the fuse element and the first switch element;
An energizing element;
One end of the cascade connection circuit and one end of the energization element are connected to the input end, and a determination circuit for determining the disconnection of the fuse element,
Including one or more trimming detection circuits including
Measurement interposed between the other end of each energization element connected in common and the first power supply, or between the other end of each cascade connection circuit connected in common and the second power supply A semiconductor integrated circuit device comprising a terminal. Each of the trimming detection circuits further comprises a control terminal,
In response to a mode signal applied to the control terminal, the first switch elements of all the trimming detection circuits are short-circuited in the normal operation mode, and only the first switch element connected to the fuse element to be tested is in the test mode. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is controlled to be short-circuited.   3. The semiconductor integrated circuit device according to claim 2, wherein the first switch element is composed of a MOS transistor, and the gate of the MOS transistor is connected to the control terminal.   3. The semiconductor integrated circuit device according to claim 1, wherein the energization element is a first resistance element.   2. The semiconductor integrated circuit device according to claim 1, wherein a circuit in which a second resistance element and a second switch element are cascade-connected is added in parallel between one end and the other end of the cascade connection circuit. . A cascade connection circuit of the fuse element and the first switch element;
An energizing element;
One end of the cascade connection circuit and one end of the energization element are connected to the input end, and a determination circuit for determining the disconnection of the fuse element,
Including one or more trimming detection circuits including
Measurement interposed between the other end of each energization element connected in common and the first power source, or between the other end of each cascade connection circuit connected in common and the second power source A method for testing a semiconductor integrated circuit device having terminals,
A test method for a semiconductor integrated circuit device, comprising: measuring only a current at the measurement terminal by short-circuiting only the first switch element in a trimming detection circuit including a fuse element to be tested.   7. The method of testing a semiconductor integrated circuit device according to claim 6, wherein a resistance value of the fuse element to be tested is obtained by measuring the current. 8. The method of testing a semiconductor integrated circuit device according to claim 7, wherein the resistance value of the fuse element is obtained by measuring the current before and after the cutting of the fuse element to be tested.

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