JPH04329025A - D/a converter - Google Patents

Abstract

PURPOSE:To reduce a period of a clock signal and to prevent switching in excess of a desired change caused when a digital data is switched. CONSTITUTION:A switch means 17 is inserted between signal sources 18 arranged as a matrix on a two-dimension plane in X and Y directions and having a prescribed analog value and an analog output terminal 19 having a connection path to each signal source 18. A latch circuit 16 is added respectively to a switch control circuit 15 controlling the switch means 17. The latch circuit 16 latches a control signal from the switch control circuit 15 and the control signal is outputted by a prescribed synchronizing signal to deliver the control signal to the switch means 17. Each switch means 17 is simultaneously controlled in response to an output signal of decoders 11, 12 and a desired analog output is obtained from an output terminal 19.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D/A converter that converts digital signals into analog signals, which require stable and high-speed operation.

0002

[Prior art] Fig. 15 shows the IEEE JOURNAL O
F SOLID-STATE CIRCUITS, VO
L. SC-21. No. 6, DECEMBER1986
"An 80-MHz 8-bit CMOS D/
It is a circuit diagram showing an 8-bit D/A converter that schematically represents the circuit configuration described in ``A Converter''.
1 to PY4) are input to latch circuits 63 and 64, respectively. The latch circuit 63 supplies latch outputs X1 to X4 in synchronization with the clock signal CK, and the latch circuit 64 supplies latch outputs Y1 to Y4 in synchronization with the clock signal CK to each switch control circuit 65 arranged in a matrix. . The switching of each switch 66 is controlled by each switch control circuit 65 . With each switch 66,
A state is established in which each analog signal source 67 constituted by a current source or resistor having an analog value and the output terminal 68 are connected or not. Through this series of processing, an analog signal OUT corresponding to Data is obtained from the output terminal 68.

FIG. 16 is a flowchart from digital data to analog signal in the operation of the circuit shown in FIG. 15, and FIG. 17 is a timing chart showing the operation of the circuit shown in FIG.
It is.

[0004] In FIGS. 16 and 17, T11 is Dat
a is transmitted to decoders 61 and 62, and PX1 to PX4
, delay time until PY1 to PY4 are output, T12
T13 is the delay time between when X1 to X4 and Y1 to Y4 are supplied from the latch circuits 63 and 64 to each switch control circuit 65 and when a control signal is output from each switch control circuit 65 to each switch 66; This is the delay time until a desired analog signal is reached after a predetermined number of analog signal sources 67 and output terminals 68 are connected. This processing time T12+T13 limits the period TS of the clock signal CK, and is an obstacle to improving the D/A conversion speed.

FIG. 18 shows the 8-bit D/A converter shown in FIG.
FIG. 2 is a circuit diagram of a specific configuration in which the converter is simplified to a 4-bit D/A converter.

In FIG. 18, Data (D0 to D3) input to decoders 61 and 62, respectively, and PX1 output from decoders 61 and 62, respectively.
~PX3, PY1~PY3 are configured so that the relationships are as shown in the truth values of FIG. The latch circuits 63 and 64 each include, for example, two stages of clocked inverters, and when the clock signal CK rises, X1 to X3, Y1
~Y3 is output.

In FIG. 15, there are 15 unit cells 71 each including a switch control circuit 65, a switch 66, and an analog signal source 67. In each unit cell 71, in order to realize monotonous increasing property, NAND/OR as shown in FIG.
A circuit 72 is configured. By inputting X1 to X3 and Y1 to Y3 to predetermined input terminals of the NAND/OR circuit 72, the respective switches 73 and 74 are controlled. A
Output S of ND/OR circuit 71 is “1”, inverter 75
When ´S via ´S is “0” (´S means an inverted signal of S), the switch 73 on the S side is turned on (the switch 74 on the ´S side is off), and the analog current source I is connected to the output terminal 68. Connected. Also, when the output S is “0” (´S=1), S
The side switch 73 is turned off (´S side switch 74
is on) This unit cell 71 is not connected to the output end 68.

In FIG. 18, Data is "1100".
” to “1011”. Figure 2
1 is a timing chart when Data is switched from "1100" to "1011", and FIGS. 22(a) and 22(b) are state diagrams showing switching images of the matrix of the unit cell 71 at that time. At “1100” (time zone T21), the matrix switch image is shown in Figure 22 (a).
)become that way. That is, in the unit cell 71, 15
Of these, only 3 switches 74 on the S side are on, and only 12 switches 73 on the S side are on. After that, “1
011'' (time zone T22), the switch image of the matrix is as shown in FIG. The switch 73 on the S side is turned on.

As mentioned above, Data changes from "1100" to "1011" at the rise of the clock signal CK, but this is because Y1 to Y3 change from "1" to "0" and
1 changes from "0" to "1". At the time of this change, due to the difference in wiring capacitance between Y1 to Y3 and X1 and the difference in the number of gates of the unit cell 71 actually connected, as shown in the timing chart of FIG. A phase difference occurs with X1, and Y1 to Y3 change from “1” to “1” faster than X1 changes from “0” to “1”.
At that time, the matrix switch image will be shown in Figure 24, and all 15 unit cells will have their S-side switches turned on.As a result, the
Output terminal 68 when switching from “100” to “1011”
The relationship between the analog signal OUT and the time t is as shown in FIG. ×I. Therefore, at the output end 68,
There is a drawback that there is a long delay time until the desired number of connected analog current sources I (11×I) is reached, and noise appears during that time.

0010

As described above, the conventional method has the drawback that the delay time until the actual analog value is reached is long, and noise appears during that time.

The present invention was made in consideration of the above-mentioned circumstances, and its purpose is to prevent switching that exceeds a desired amount of change that occurs when digital data is switched, eliminate noise, and improve analog An object of the present invention is to provide a D/A converter that realizes a reduction in conversion speed.

0012

[Means for Solving the Problems] The D/A converter of the present invention includes a decoder in the X direction and the Y direction to which digital signals are input, and decoders arranged in a matrix on a two-dimensional plane in the X direction and the Y direction. switch means each inserted between a signal source having a predetermined analog value arranged therein and an analog output end having a connection path to each of the signal sources and each of the signal sources; The output signals of the X-direction and Y-direction decoders arranged in a matrix with the same number as the signal sources are taken in, and control signals for controlling the respective switch means are generated in accordance with the output signals of the decoders. a switch control circuit, and a latch that is added to each of the switch control circuits, latches a control signal from the switch control circuit, and transmits the control signal from the switch control circuit to each of the switch means by a predetermined synchronization signal. It is characterized by being equipped with a circuit.

[0013]

[Operation] In this invention, by providing a latch circuit in each switch control circuit that controls the switch means,
The period of the clock signal that limits the D/A conversion speed is shortened. In addition, this latch circuit transmits the output signal from the switch control circuit to the switch means at the same timing, so when the digital signal switches, it is suppressed to only the desired change, and switching noise such as glitches is prevented at the output end. Prevented.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described by way of embodiments with reference to the drawings.

FIG. 1 shows 8b according to a first embodiment of the invention.
FIG. 2 is a circuit diagram showing the configuration of an itD/A converter. Digital data is sent to decoder 11 and decoder 12
and their outputs (PX1 to PX4, PY
1 to PY4) are input to latch circuits 13 and 14, respectively. The latch circuit 13 supplies latch outputs X1 to X4 in synchronization with the clock signal CK, and the latch circuit 14 supplies latch outputs Y1 to Y4 in synchronization with the clock signal CK to each switch control circuit 15 arranged in a matrix. . The output from each switch control circuit 15 is supplied to a respective latch circuit 16 provided therein. The output of the latch circuit 16 controls the switching of each switch 17 in synchronization with the clock signal CK. Each switch 17
Accordingly, an analog signal corresponding to Data can be obtained from the output end 19 depending on whether each analog signal source 18 constituted by a current source or a resistor having an analog value is connected to the output end 19.

FIG. 2 is a flowchart showing the operation of the circuit shown in FIG. 1 from digital data to output of an analog signal, and FIG. 3 is a timing chart showing the operation of the circuit shown in FIG.

In FIGS. 2 and 3, T1 is Data
is transmitted to decoders 11 and 12, and PX1 to PX4, P
The delay time T2 until Y1 to PY4 are output is that X1 to X4 and Y1 to Y4 are supplied from the latch circuits 13 and 14 to each switch control circuit 15, and each switch control circuit 1
5 until the control signal is output to each latch circuit 16, T3 is the delay time T3 from when the switch 17 is operated by the control signal output from each latch circuit 16, and each analog signal source 18 and output terminal 19 are connected by a predetermined number of times. This is the delay time until the signal is connected and the desired analog signal is reached.

Looking at the operating waveform of the output terminal 19, switching is performed simultaneously with the clock signal CK, and a desired analog signal is reached. As a result, the clock signal CK
The processing time for limiting the period TS of the clock signal CK becomes only T3, and the period TS of the clock signal CK is shortened. This results in
D/A conversion speed is improved.

FIG. 4 is a circuit diagram of a specific configuration in which the 8-bit D/A converter of the above embodiment is simplified to a 4-bit D/A converter. The same parts as in FIG. 1 are given the same reference numerals.

In FIG. 4, Data (D0 to D3) input to the decoders 11 and 12, respectively, and PX1 to PX1 to output from the decoders 11 and 12 accordingly.
The relationship between PX3 and PY1 to PY3 is configured to match the truth value shown in FIG. 19 described above. Decoder 11 is D
NAND gate 11- which inputs D2 and D3 of ata
1 and D2, and a NOR gate 11-3 that receives D2 and D3. Decoder 12
is NAND gate 1 which inputs D0 and D1 of Data.
Inverter 12-2, D0, D that inputs 2-1, D1
It consists of a NOR gate 12-3 that inputs 1.

The latch circuits 13 and 14 each have, for example, two
Stage clocked inverters 13-1 to 13-3, 14
-1 to 14-3, and outputs X1 to X3 and Y1 to Y3 at the rising edge of the clock signal CK.

Each of the unit cells 21 (U1 to U15) consisting of the switch control circuit 15, latch circuit 16, switch 17, and analog signal source 18 in FIG.
There are 5 of them.

FIG. 5 is a circuit diagram showing an example of the configuration of each unit cell 21. In a NAND/OR circuit 24 made up of an OR circuit 22 and a NAND circuit 23, each signal is input to a predetermined input terminal. Each output signal from the latch circuit 14 or the ground voltage GND is input to one input terminal of the OR circuit 22 . The other input terminal of the OR circuit 22 receives each output signal from the latch circuit 14 or the ground voltage GND. One input terminal of the NAND circuit 23 receives each output signal from the latch circuit 13 or the power supply voltage V.
cc is input. The output terminal from the OR circuit 22 is connected to the other input terminal of the NAND circuit 23.

At the output end of the NAND/OR circuit 24, there are two clocked inverters 25 and 26 controlled by signals φ and ´φ (´φ means an inverted signal of φ) corresponding to the clock signal CK. connected in series. The output end of the clocked inverter 26 supplies the signal 'S and the signal S via the inverter 27 to the respective switches 28 and 29. A switch 28 on the signal 'S side is inserted between the power supply Vcc and the analog current source I. A switch 29 on the signal S side is inserted between the analog signal output terminal 19 and the analog current source I.

By inputting X1 to X3 and Y1 to Y3 to predetermined input terminals of the NAND/OR circuit 24, the respective switches 28 and 29 are controlled. Signal 'S' output via NAND/OR circuit 24 and clocked inverters 25 and 26 ('S means an inverted signal of output S)
is "0" and the signal S via the inverter 27 is "1", the switch 29 on the S side is turned on (the switch 28 on the S side is off), and the analog current source I is connected to the output terminal 19. Further, when the signal S is "0"('S is "1"), the S-side switch 29 is turned off ('S-side switch 28 is on), and this unit cell 21 is not connected to the output end 19.

In FIG. 4, Data is “1100”
Let us consider the case where the data is switched from "1011" to "1011".

FIG. 6 shows that Data changes from “1100” to “1”.
7(a) and 7(b) are state diagrams showing the switching image of the matrix of the unit cell 21 at that time.

[0028] Data is from “1100” to “1011”
”, Y1 to Y3 change from “1” to “0”,
1 changes from "1" to "0". In this invention, FIG.
Even if a phase difference occurs between Y1 to Y3 and X1 as shown in , the signal in which Y1 to Y3 and X1 are completely switched (Y1 to
Y3 is "0" and X1 is "1") are latched by the clocked inverters 25 and 26 shown in FIG. 5, and the switches 28 and 29 are controlled at the next rising edge of the clock signal CK. As a result, among all the unit cells 21 (U1 to U15), only U13 changes the S and 'S signals, and a desired analog signal is output to the output terminal 19.

In this way, for example, if Data is “110
When switching from "0" to "1011", the number of analog current sources I connected to the output terminal 19 changes from 12×I to 11×I, as shown in FIG. 7(a) to FIG. 7(b). Therefore, at the output terminal 19, the desired change (12×I to 1
1×I) cannot be exceeded. Therefore, analog output can be obtained faster without noise appearing while the output is stabilized as in the conventional case.

There are various modifications of the unit cell 21 shown in FIG. 5 in the above embodiment, the configurations of which are shown below.

In FIGS. 8(a) to 8(e), the basic logic circuit is a NAND/OR circuit similar to that in FIG. 6. However, the way the clock signal is applied is different.

FIG. 8(a) shows the NAND circuit 2 in FIG.
3 is replaced with a clocked NAND circuit 31, and a clock signal φ or 'φ is applied. The output of the clocked NAND circuit 31 is the signal 'S and the inverter 2
7, and the respective switches 28 and 29 are controlled by these signals.

FIG. 8B shows that the output of the clocked NAND circuit 31 in FIG. These signals control the respective switches 28 and 29.

In FIG. 8(c), the output of the clocked NAND circuit 31 to which 'φ in FIG. 8(a) is input is input to the clocked inverter 35.
The signal S is output at the timing of φ given to the switch 5, and the signal 'S is output via the inverter 27.
29 is controlled.

FIG. 8(d) shows a configuration in which the clocked inverter 25 in FIG. S is output, and further a signal S is output via the inverter 27. These signals control the respective switches 28 and 29.

In FIG. 8(e), an inverter 37 is inserted between the serially connected clocked inverters 25 and 26 in FIG. Furthermore, a clocked inverter 38 is provided in place of the inverter 27, and its input terminal is connected to the output terminal of the inverter 25. Clocked inverter 38 is given φ so that it is controlled simultaneously with clocked inverter 26. The output of the clocked inverter 26 is the signal S, and the output of the clocked inverter 38 is the signal 'S.
With these signals, the respective switches 28 and 29 are activated.
is controlled.

FIGS. 9(a) to 9(f) show an NA whose basic logic circuit is composed of the OR circuit 22 and the NAND circuit 23 of FIG.
In place of the ND/OR circuit 24, a NOR/AND circuit 43 consisting of an AND circuit 41 and a NOR circuit 42 is configured. FIG. 9(a) shows a circuit configuration corresponding to FIG. 5, and FIG. 9(b)
8(f) have circuit configurations corresponding to FIGS. 8(a) to 8(e), respectively.

In each of FIGS. 10(a) to 10(d), the basic logic circuit is similar to the NAND/OR circuit 24 in FIG. 5, with one output signal and one switch connected to the analog signal source. This is the configuration.

In each of FIGS. 11A to 11D, the basic logic circuit is similar to the NOR/AND circuit 43 of FIG. 9, with one output signal and one switch.

FIG. 12 is a circuit diagram showing a second embodiment of the present invention. Compared to FIG. 1, the configuration is such that latch circuits 13 and 14 for latching the outputs (PX1 to PX4, PY1 to PY4) of decoder 11 and decoder 12 are omitted. Compared to FIG. 1, there is no latch circuit 13, 14, so high-speed operation is possible.

FIG. 13 is a circuit diagram showing a third embodiment of the present invention. R-segment type 4-bit D/A
This invention is applied to a converter. decoder 61,
The relationship between the data (D0 to D3) inputted to each of the decoders 62 and X0 to X3 and Y0 to Y3 outputted from the decoders 61 and 62 accordingly corresponds to the truth value shown in FIG. There is.

The outputs X0 to X3 from the decoder 61 and the outputs Y0 to Y3 from the decoder 61 are supplied to the input terminals of each predetermined AND circuit 63 in the matrix. A latch circuit 64 is provided at the output end of each AND circuit 63, respectively. The output of each AND circuit 63 is latched by a latch circuit 64 synchronized with clock signal CK. Switch 65 is controlled by the output signal of latch circuit 64. The output terminal 68 is controlled so that each resistor 66 has a predetermined analog value by controlling each switch 65 to turn on and off.
connected to.

[0043]

[Effects of the Invention] As explained above, according to the present invention,
The latch circuit provided in each matrix makes it possible to converge to the desired analog value at the same time as the clock signal rises.Moreover, when the digital signal switches, the analog value is suppressed to only the desired change.
Switching noise such as glitches is prevented. This makes it possible to provide a D/A converter with stabilized D/A conversion and increased speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a configuration according to a first embodiment of the present invention.

FIG. 2 is a flow chart of the operation of the circuit in FIG. 1 from digital data to output of an analog signal.

3 is a timing chart showing the operation of the circuit shown in FIG. 1. FIG.

FIG. 4 is a circuit diagram showing a specific configuration of the present invention, which is a simplified version of FIG. 1;

FIG. 5 is a circuit diagram showing an example of a specific configuration of the unit cell in FIG. 4.

6 is a timing chart showing the circuit operation of FIG. 4. FIG.

FIG. 7 is a state diagram showing a switch image in the unit cell matrix of FIG. 4;

8 is a circuit diagram showing a first modification group of the unit cell of FIG. 4. FIG.

9 is a circuit diagram showing a second modification group of the unit cell of FIG. 4. FIG.

10 is a circuit diagram showing a third modification group of the unit cell of FIG. 4. FIG.

11 is a circuit diagram showing a fourth modification group of the unit cell of FIG. 4. FIG.

FIG. 12 is a circuit diagram of a configuration showing a second embodiment of the invention.

FIG. 13 is a circuit diagram showing a third embodiment of the present invention.

14 is a diagram showing truth values showing the operation of a part of the circuit shown in FIG. 13;

FIG. 15 is a circuit diagram showing the configuration of a conventional D/A converter.

FIG. 16 is a flowchart from digital data to output of an analog signal in the operation of the circuit in FIG. 15;

17 is a timing chart showing the circuit operation of FIG. 15. FIG.

18 is a circuit diagram showing a specific configuration of the present invention, which is a simplified version of FIG. 15. FIG.

FIG. 19 is a diagram showing truth values of some circuit operations in FIG. 18;

20 is a circuit diagram showing an example of a specific configuration of the unit cell in FIG. 18. FIG.

21 is a timing chart showing the circuit operation of FIG. 18. FIG.

22 is a state diagram showing a switch image in the unit cell matrix of FIG. 18; FIG.

23 is a timing chart showing problems in the circuit operation of FIG. 18; FIG.

24 is a state diagram showing a switch image in the unit cell matrix of FIG. 18 at the problem point in FIG. 23; FIG.

25 is a characteristic diagram showing a change in the output terminal with respect to time, showing a problem in the operation of the circuit shown in FIG. 18; FIG.

[Explanation of symbols]

Claims (1)

[Claims] 1. A decoder in the X and Y directions to which digital signals are input, and a signal source having predetermined analog values arranged in a matrix on a two-dimensional plane in the X and Y directions. switch means each inserted between each of the signal sources and an analog output terminal having a connection path to each of the signal sources; a switch control circuit which takes in the output signals of the decoders in the direction and the Y direction, and generates control signals for controlling the respective switch means according to the output signals of the decoder; and a switch control circuit added to each of the switch control circuits. and a latch circuit that latches a control signal from the switch control circuit and transmits the control signal from the switch control circuit to each of the switch means by a predetermined synchronization signal. converter.