JPH05197619A - Memory control circuit for multi-cpu - Google Patents

Abstract

PURPOSE:To prevent the performance of an entire system from being lowered by reducing access competition between CPUs in the computer system provided with a shared memory in a multi-CPU system. CONSTITUTION:A memory 30 is divided into two first and second memory blocks 10 and 11, and a system for allocating the address spaces of the respective memory blocks is set as an interleave system. When writing data, data in CPU 1 and 2 are respectively selected by multiplexers 3 and 4 and when reading data, data in the memory blocks 10 and 11 are respectively selected by multiplexers 5 and 6.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a multi-CPU memory control circuit, and more particularly to a multi-CPU memory control circuit in a computer system in which a plurality of CPUs share a memory.

[0002]

2. Description of the Related Art A conventional memory control circuit of this type has the structure shown in FIG. In the figure, the two CPUs 1 and 2 can commonly use the memory 30. When an access conflict occurs in which both the CPUs 1 and 2 simultaneously access the memory 30, the timing controller 31 detects the access conflict state and controls the memory controller 32 to access the CPU having a high priority. The so-called exclusive control operation that gives priority to is performed.

As described above, in the conventional memory control circuit, when one CPU is accessing the memory, the other CPU cannot access and is stopped, so that the performance of the entire system is deteriorated. There is a drawback that

[0004]

SUMMARY OF THE INVENTION Therefore, the present invention has been made to solve the drawbacks of the prior art, and an object of the present invention is to enable a plurality of CPUs to access a memory at the same time, and It is an object of the present invention to provide a memory control circuit for a multi-CPU, which has improved performance.

[0005]

A memory control circuit for a multi-CPU according to the present invention comprises a memory having a plurality of address spaces which are commonly accessible from the first and second CPUs and whose address allocation method is an interleave method, and Means for selectively deriving access addresses from the first and second CPUs to the respective address spaces, and respective access data between the first and second CPUs and the respective address spaces, respectively. When the access means of the alternative CPU and the access addresses of the first and second CPUs compete for one of the address spaces, the predetermined C
And means for waiting and controlling the access of the PU.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. First, the memory will be described. In the embodiment of the present invention, the memory 30 is composed of two memory blocks 10 and 11. The allocation of each address space of these two memory blocks is so-called interleaved as shown in FIG. It is a method.

That is, the address space of the first memory block is made up of an address group in which AB1 = "0"("AB1" indicates the second lowest address bit),
In decimal notation, the address group consists of 4n addresses and 4n + 1 addresses (n is a positive integer including 0). The address space of the second memory block consists of an address group for which AB1 = "1". Similarly, in decimal notation, addresses 4n + 2 and 4n
It consists of a group of addresses at +3.

In FIG. 3, the hexadecimal system of 4 bits is shown, and H is added at the end to show that it is the hexadecimal system, and the same applies hereinafter.

In the present embodiment, the word width of the memory access unit is 8 bits × 2. Therefore, for example, the CPU accessing the address 0000H means 0000.
It means accessing not only H address but also 0001H address at the same time. In other words, the CPU needs 2n for one access.
It means that the address and the address 2n + 1 (decimal notation) are simultaneously accessed.

In FIG. 1, the multiplexer 3 includes a first
By the instruction from the timing controller 9 generated in response to the write instruction to the memory block 10 of
The write data from the CPU 1 or 2 is selected and output. Similarly, the multiplexer 4 receives the instruction from the timing controller 9 generated in response to the write instruction to the second memory block 11, and then the CPU 1 or 2
Select the write data from and output.

The multiplexer 5 selects and outputs the read data from the first memory block 10 or the second memory block 11 according to an instruction from the timing controller 9 generated in response to the memory read command from the CPU 1. .. Similarly, the multiplexer 6 receives a command from the timing controller 9 generated in response to a memory read command from the CPU 2, and then the first memory block 1
0 or read data from the second memory block 11 is selected and output.

The multiplexer 7 selects and outputs an address from the CPU 1 or 2 according to an instruction from the timing controller 9 generated in response to a memory access (read / write) command for the first memory block 10. Similarly, the multiplexer 8 receives an instruction from the timing controller 9 generated in response to a memory access instruction for the second memory block 11,
The address from the CPU 1 or 2 is selected and output.

The memory controllers 12 and 13 control each of the first and second memory blocks 10 and 11 according to an instruction from the timing controller 9.

In such a configuration, the CPUs 1 and 2 start memory access at the same time, and the CPU 1 continuously addresses from 0000H to 0007H and the CPU 2 from 1000H to 1007H (8 bits x
2) A case of memory access with a word width will be described. However, it is assumed that the CPU 1 has a higher memory access priority than the CPU 2, and the timing controller 9 controls the contention.

The CPU 1 sets AB1 = "0" when accessing the memory block at address 0000H. Further, the timing controller 9 instructs the multiplexers 3 and 7 to select the data and address from the CPU 1 and the memory controller 12 to start the memory access.

When writing, the multiplexer 3 is enabled, and when reading, the multiplexer 5 is enabled. The address flow is CPU 1 → multiplexer 7 → memory controller 12.

Further, the data flow is such that the CPU 1
→ Multiplexer 3 → Memory block 10 and when reading, memory block 10 → Multiplexer 5 →
It becomes CPU1. At this time, since the CPU 1 is accessing the memory block 10 even if the CPU 2 tries to access the memory at address 1000H, it is stopped by the timing controller 9. CP in this way
U1 ends the memory access to address 0000H.

Next, the CPU 1 starts the memory access at the address 0002H. On the other hand, the CPU 2 is informed by the timing controller 9 that the CPU 1 is not using the memory block 10,
Start memory access to address 0H.

Since the CPU 1 accesses the memory at the address 0002H, AB1 is set to "1", and the CPU 2 makes an access to the memory at the address 1000H, AB.
Set 1 to “0”. Further, the timing controller 9 uses the multiplexer 4 to access the memory of the CPU 1.
Instruct to select data from CPU1,
The multiplexer 8 is instructed to select the address from the CPU 1, and the memory controller 13 is instructed to start the memory access.

Further, the timing controller 9 enables the multiplexer 4 to select the data of the CPU 1 to enable the output when writing, and enables the multiplexer 5 to select the data of the memory block 11 to enable the output when reading.

Further, for the memory access of the CPU 2, the multiplexer 3 is instructed to select the data from the CPU 2, and the multiplexer 7 is instructed to select the address from the CPU 2, and the memory controller 12 starts the memory access. To instruct.

At the time of writing, the multiplexer 2 has the CPU 2
Data is selected and the output is enabled, and at the time of reading, the multiplexer 6 selects the data in the memory block 10 and the output is enabled. The address flow at this time is CPU1 → multiplexer 8 → memory controller 13, and CPU2 → multiplexer 7 → memory controller 12.

The data flow of the CPU 1 is C at the time of writing.
PU1 → multiplexer 4 → memory block 11, memory block 11 for reading → multiplexer 5 → CPU
It becomes 1. The data flow of CPU2 is CPU when writing
2 → multiplexer 3 → memory block 10, and memory block 10 for reading → multiplexer 6 → CPU 2.

In this way, the memory is alternately used, and C
PU1 is from 0000H to 0007H, CP
U2 completes each memory access from address 1000H to address 1007H.

The timing of the above series of operations is shown in FIG. As can be seen from FIG. 2, it can be seen that the CPU1 and the CPU2 can simultaneously access the memory. At the first access timing, both CPUs 1 and 2 are in an access contention state with respect to the first memory block 10,
The access of the CPU 2 having a low priority is delayed only while the access of the CPU 1 to the first memory block 10 is completed.

In the above embodiment, the memory is made into two memory blocks, and the address space allocations are given to each other in a discrete manner so as to be continuous as a whole. If divided into blocks and similar address allocation is performed, 1
The probability of occurrence of access competition from multiple CPUs for one memory block is small and efficient, but
It is unavoidable that the timing control becomes complicated.

It is obvious that the CPU 1 can be applied not only to two CPUs but also to three or more CPUs.

[0029]

As described above, according to the present invention, since a plurality of CPUs can simultaneously access the memory, it is possible to improve the performance of the multi-CPU computer system.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing memory access timing according to the embodiment of the present invention.

FIG. 3 is a diagram showing an example of address allocation of a memory block according to an embodiment of the present invention.

FIG. 4 is a block diagram of a conventional multi-CPU memory control circuit.

[Explanation of symbols]

 1, 2 CPU 3-8 Multiplexer 9 Timing controller 10, 11 Memory block 12, 13 Memory controller 30 Memory

Claims (1)

[Claims] 1. A memory having a plurality of address spaces which are commonly accessible from a first and a second CPU and whose address allocation method is an interleave method;
And means for selectively deriving access addresses from the second CPU to each of the address spaces, and the first
And means for selectively connecting respective access data between the second CPU and each of the address spaces, and access addresses of the first and second CPUs to one of the address spaces. A memory control circuit for a multi-CPU, comprising means for waiting and controlling access of a predetermined CPU when there is a conflict.