JPH10293782A - Layout compiling method and design system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform compilation to integrated logic and a DRAM system on a single chip from the hardware description language and wiring description of design composed of a DRAM macro and a logic macro by integrating logic and a DRAM memory to the same chip. SOLUTION: From a single processor memory chip for which a processor 21 is connected to a DRAM 22 by on-chip mutual connection 23, off-chip mutual connection disappears. Thus, by DRAM I/O and internal control, a memory data transfer rate utilizable for the processor 21 is raised for many digits. By integrating the processor 21 and the DRAM 22 to the same chip, the length of the on-chip mutual connection 23 and a capacitive load are substantially reduced and optimization is performed further by making the length of a wire shortest. As a result, a system clock speed is accelerated further and performance is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to single-chip implementations of logic and memory components, and, more particularly, to a hardware description language (HDL) for a design comprising logic components and memory components. )
System-on-chip layout automation method for converting (compiling) a layout on a silicon chip with optimized floor plans, macros and layout structures for logical and dynamic random access memory (DRAM) circuits About.

[0002]

2. Description of the Related Art The computational speed of processors (eg, MIPS, or Millions of Instructions per Instructions), has been demonstrated in today's microprocessors and main memory.
The performance gap, which is the difference between memory access data transfer rate (measured in econd) and memory access data rates, is increasing with each new generation of chips. Bandwidth bottlenecks between the graphics controller (processor) and the frame buffer (memory) limit the performance of conventional display subsystems.

A major reason for the above problems in systems with processors and dynamic random access memories (DRAMs) is that the processor and memory chips are implemented on separate chips. It is. Other attempts have been made to solve these problems. In other words, it is based on a multilayer ceramic module (MCM) technology or a silicon-on-insulator (SOI) technology that collectively stores individual silicon chips. However, this is because the processor (logic) and the memory (DRAM) are implemented on different chips, so that the limited bandwidth between the processor and the memory and the large capacitive load appearing on off-chip interconnects is reduced. It does not address the issue of still limiting system performance.

[0004]

Accordingly, it is an object of the present invention to provide a hardware description language for a design comprising a DRAM macro and a logic macro (eg, a gate array, a standard cell, a custom design circuit, a microprocessor, a test circuit). (HDL) and wiring description to provide a layout compiler for compilation into integrated logic and DRAM systems on a single chip.

It is another object of the present invention to provide a layout compiler for creating a physical structure (floor plan) of an integrated logic / DRAM chip from a system / circuit wiring description.

Still another object of the present invention is to provide a memory capacity,
From basic DRAM building blocks, physical structures, circuits, and embedded growable DRAM macros with varying amounts of banking and input / output (I / O) bandwidth, a variety of addresses for a wide range of integrated logic / DRAM applications Integrated logic / DRA for creating specified techniques, various modes of operation (eg, asynchronous, synchronous, page, pipeline and interleaving), and timing requirements
An object of the present invention is to provide a DRAM compiler / configurator which is a main component of a compiler design system for M chips.

[0007] Still another object of the present invention is to provide a DRAM.
To provide an on-chip interconnect between macros and logic macros to provide a layout method that solves the bandwidth bottleneck problem in prior art discrete multi-chip implementations for processors and memory systems. .

[0008]

According to the present invention, a logic processor and a DRAM memory are integrated on a single chip. This solves the processor / memory performance gap and bandwidth issues discussed above. Logic and DR
By integrating the AM memory with the same chip, the difference between the maximum data processing speed of the logical processor and the maximum data access speed of the DRAM memory can be minimized. The disclosed layout method eliminates the off-chip drivers and the large capacitive loads that appear on off-chip interconnects in prior art discrete multi-chip implementations for processors and memory systems. Low power loss is a direct result of the integrated logic / DRAM chip during high frequency operation.

[0009] The layout method according to the present invention eliminates the large capacitive load between off-chip drivers and processors and memories. As a result, the clock frequency of the integrated processor and memory chips can be further increased to improve system performance. This layout method results in an on-chip interconnection between the DRAM macro and the logic macro, which alleviates the pin density constraints in conventional DRAM packages for processor and memory systems. Further, the layout method creates an internal layout of the DRAM macro that is accessible for modification. As a result, the overall design of the processor and memory system can be further enhanced in terms of performance and customized for a particular application. Further, the layout method allows for the flexibility to add control logic macros / circuits to optimize the overall performance and operation of the integrated processor and memory chip layout.

[0010]

DETAILED DESCRIPTION OF THE INVENTION Referring to the drawings, and in particular to FIG. 1, a conventional multi-chip processor and memory system is shown, in which a processor 1 is shown.
1 is connected by an off-chip interconnect 13 (e.g., a system bus) to a memory 12, which is typically comprised of a DRAM chip. This system suffers from limited bandwidth due to off-chip interconnects and high power loss due to large capacitive additions.

FIG. 2 shows a single processor memory chip in which processor 21 is connected to DRAM 22 by on-chip interconnect 23. Since the off-chip interconnect is gone as shown in FIG.
With I / O and internal control, the memory data transfer rate (bits per unit time) available to the processor can be increased by orders of magnitude, so that bandwidth issues are almost eliminated.

Although the power loss is large due to the large capacitive load appearing in the off-chip interconnect as shown in FIG. 1, the integration of the processor and DRAM on the same chip as shown in FIG. Power losses can be significantly reduced because the connection length and capacitive load are much smaller and can be further optimized by minimizing the wire length. As a result, the system clock speed can be further increased and performance can be improved.

FIG. 3 shows a logic 31 of a plurality of chips and a DRAM.
1 shows a conventional system in which 32 is connected to a common bus 33 such as a system bus. In contrast, DRAM
The various forms in which a chip and a logic chip can be combined into a single chip (ie, chip floor plan)
Are shown in FIGS. 4 to 7. FIG. 4 shows the basic structure when placing DRAM components and logic components on a single chip.
The logic portion includes one or more processors, control units, and various subsystems such as graphic and digital signal processors. The DRAM part implements the memory / cache for the logical part.
The DRAM portion and the logic portion are connected by a high bandwidth on-chip bus. Other components such as chip I / O interface and clock generation are also included.

FIGS. 5, 6 and 7 show various variations of the integrated DRAM / logic chip. Figure 5 shows that DRAM satisfies form factor, granularity, and optimization.
FIG. 4 illustrates an integrated DRAM / logic chip that has been split into several DRAM macros for various reasons, such as increasing the bandwidth of the AM.

FIG. 6 shows a microprocessor (μP), two-level caches (CA1 and CA2), DRAM-based memory, system and bus control units, a digital processor (DP) and a video engine (MP) for multimedia applications. VE), an analog subsystem (AS) for communications and graphics applications, and a computing system in which a clock subsystem and a chip I / O interface are integrated on a chip.

FIG. 7 shows an array of processing elements (P) each comprised of logic elements and DRAM elements for parallel processing applications such as graphics, hardware simulation, and the like. Each processing element P is a local integrated logic / DRAM unit, a logical processor, a control unit, a local DRAM memory and a local
It consists of a bus. Processing elements P are interconnected by a two-dimensional global bus. The system control unit acts as an overall system control for the chip.

Conventional memory design requires a time consuming process that requires many man-years of manual work to fully optimize the layout. This method is very effective for mass production. Recently, by creating new architectures such as particularly wide I / O, synchronous interfaces, pipelines and interleaves, and multi-bank architectures, various D
RAM chips are trying to match the performance of processors.

The method described herein allows a DRAM macro structure to meet the requirements of a particular application. This is because the internal structure and layout of the DRAM macro can be accessed on-chip, so that the DRAM can be adapted to the performance and functional expansion by the corresponding logic part.
This is because the structure can be reconfigured. FIG. 8 shows a system including a discrete DRAM chip 52 and a logic chip 53. In the illustrated example, m DRs
There is an AM chip 52, each chip has n bits, and the I / O of each DRAM chip is b bits wide. Thus, there are n × m bits of DRAM, and the system bandwidth is f × b (where f is the system clock frequency).

FIG. 9 illustrates the different ways in which the DRAM in the discrete case can be integrated on a single chip in the form of several DRAM macros. The configuration of the on-chip DRAM macro is (1) M on-chip DRAM macros,
(2) Y sub DRAM macros in each DRAM macro, (3) X basic DRs in each sub DRAM macro
AM building blocks (A), (4) B I / O data bits per macro, (5) External on-chip address, data, DRAM macro driving control bus, such as RAS, CAS, CE, etc., and Internal bit
The output drive power of the driver in the DRAM macro for lines, word lines, etc. can be customized. Maximum number of I / Os for DRAM macro B
_max is given by B _max = X I _max , where I _max is the maximum I / O that the basic building block (A) can provide.

M DRAs in an integrated DRAM / logic chip
Assume that there is an M macro. The macros are divided into K groups (banks) so that at any given cycle, M / K macros in a particular bank are active. The overall on-chip DRAM I / O width is B
M / K bits, which is much larger than b bits in discrete ones. When the integrated DRAM / logic chip operates at the clock frequency F, the DRAM
/ The bandwidth of the logical data bus will be FBM / Kbit / sec. F is generally larger (higher speed) than f (bus clock frequency in a discrete multi-chip configuration), and the integrated DRAM I / O width B is FBM /
K bits / sec, which is a discrete but b
Larger, so the overall data
The bus bandwidth is much higher than discrete but fb bits / sec.

FIG. 10 shows a variable capacity (X, Y, a bits) and variable I / O width (B bits) (where a is the number of bits in the basic building block A) two-dimensionally growable and flexible. FIG. 3 is a block diagram of a DRAM macro. DR
AM macro, eg 1Mb, 2Mb, 3M
b,. . . , 16 Mb are made possible by customizing the row decoder and address lines of the DRAM macro. This is not possible if the DRAM is implemented as a discrete chip. Each DR
By configuring I / O connections of sense amplifiers, column decoding logic, and peripheral circuits (located below the DRAM macro shown in FIG. 10) in the sub-array of the AM sub-macro, for example, X1, X4, X8 , X16, etc., can be generated with a variable I / O width (B bits). As the x and y dimensions of the DRAM macro are changed, the bit line and word line drivers are adjusted accordingly for the changes in the loading of the resistors and capacitances. The driver power of the output driver of the DRAM macro is programmed to drive the control bus such as external on-chip address, data, RAS, CAS, CE, etc. when the loading of the resistance and capacitance is changed.

The address lines of the online DRAM macro can be accessed directly and in parallel by a custom row decoder, rather than the multiplexing of discrete DRAMs due to address I / O pin count constraints. As a result, the on-chip DRAM has the advantage that the address setting time is shorter than that of a discrete multi-chip DRAM / logic configuration.

By adding pipeline registers to the custom peripheral portion of the on-chip DRAM macro (see FIG. 10), the read and write access times of a conventional discrete DRAM can be reduced by several small time steps operating in "synchronous" mode. Can be divided into Therefore, the on-chip DRAM macro can operate at a clock frequency several times faster, and also stores data in logic and DRA.
M can be read and written at much faster speeds. The ratio of read / write access time to synchronous pipeline cycle time is a design parameter of the chip architecture for that DRAM macro.

In accordance with the method described herein, modification of the interface between the processor / logic and the DRAM can be performed using ADDR, RAS and CAS timing, DRA.
This can be performed in a manner that meets the requirements specific to the DRAM macro, such as the timing and clock frequency of the M control signals (WE, CE). D for synchronous, asynchronous, page mode, etc.
By designing the logic / DRAM interface circuit, the different operation modes of RAM can be used to
Can be incorporated into the architecture. As a result, the overall performance between logic and DRAM is further improved.

The method described herein uses a logic macro and D
Since the RAM macro and the RAM chip can be integrated on the same chip and the logic component and the DRAM component can be accessed in the integration process, optimization is performed according to the combined operation and overall performance.

The method described herein addresses the noise problem associated with integrating logic and DRAM macros on the same silicon chip. When the logic is arranged on a different chip from the DRAM, the dI /
dt switching noise is isolated from DRAM cells and sense amplifiers. When the logic macro and the DRAM macro are placed on the same chip, switching noise from the logic circuit propagates / couples through the power supply bus, and affects the proper operation of the DRAM circuit due to the deterioration of the voltage of the DRAM voltage source. A special structure is described for decoupling capacitance and routing the power bus to isolate noise coupling between logic and DRAM circuits (see below with reference to FIGS. 14 and 17). .

FIG. 11 shows four DRAM macros (eg, 4-6 Mbits), gate array logic macros, custom macros, phase locked loops, and others such as chip I / O drivers for low power video display applications. Logic composed of support macros for
1 shows a chip layout structure of a DRAM chip. DR
The AM macro acts as a frame buffer as found in a discrete multichip implementation.

FIG. 12 illustrates a method and system for system-on-chip layout compilation according to the present invention. Starting from a hardware description language (HDL) of a chip design consisting of memory components and logical components through a series of computer aided design (CAD) steps,
"Compile" HDL into chip floor plan, macro layout, and finally complete layout of chip
can do.

Control macro, processor macro, DRA
The HDL and wiring of the design consisting of M macros, chip I / O, clock macros, and various analog, graphic, and digital signal processing subsystems are compiled into a single chip layout. Processor and DRA
Although M was conventionally manufactured on separate chips, the present invention describes the general physical structure (floor plan) of a combinational logic / DRAM chip. The method according to the present invention generates the physical structure of DRAM macros and logic macros, and accommodates various DRAs for low power loss and short cycle times.
Create and optimize low capacitance on-chip interconnections between M and logic macros. The method according to the invention also produces an overall chip layout for the integrated logic / DRAM chip.

Conventional design systems primarily address the problem of placing the processor and logic on one chip and the DRAM on another single chip, as described herein. It does not address the problem of combined logic and DRAM logic. The layout of DRAM chips has been mainly done manually to achieve high density and high yield for mass production of DRAM. The present invention is a series of computer-aided design steps for configuring physical structures such as DRAM macro memory capacity, I / O width, access time, R / W mode, etc. according to requirements for integrated logic / DRAM chips. The method also creates the structure / layout of a logic macro that works with the DRAM macro on a single chip.

The method also generates from the hardware description language of the design the overall physical structure (floor plan) of the integrated logic / DRAM chip, including individual DRAM macros and individual logic macros. The method assembles various DRAM macros and logic macros into an integrated logic / DRA
The final layout of the M chips is also formed.

The integrated system on the chip, as described above,
It consists of several functionally different entities (ie macros). Microprocessor, graphics /
Some entities, such as video controllers and digital signal processors, have well-defined and well-defined internal base cores that do not change during design integration to form complex chips .

As shown in FIG. 12, a DRAM configurator / compiler 901 receives an input from a DRAM memory subsystem specification 902 and, based on a primitive DRAM array, a sense amplifier, a decoder, etc., a DRAM sub-macro and sub-array, row And the overall circuit and layout of the DRAM macro by configuring column decoders, peripheral timing and I / O circuits to produce an integrated DRAM and logic system, DRAM macro capacitance and corresponding address lines, synchronous pipeline lines Meet function and timing requirements for clock speed, I / O width, etc. The output of DRAM configurator 901 is three databases,
That is, it is supplied to the layout database 906 via the hardware description database 903, the logic and circuit database 904, and the custom layout function 905. Uses modular and parametric techniques to meet timing and functional requirements for the required range of integrated DRAM / logic applications because DRAM macros are not as optimized as discrete DRAMs as a single unique design For this purpose, the circuit and layout of the DRAM macro are defined and created.

The bus and interface synthesizer 907 receives an input from the I / O specification 908, and executes various logics on the chip and logics related to a system bus and logics necessary for connecting ("sticking") the DRAM macros. Synchronize. In addition to signal connectivity information between macros as described in HDL, logic polarity, timing information between various macros and input / output loading,
The loading of the capacitance and the RC delay timing requirements of the bus are input to the synthesizer. The combiner combines the buffers, drivers and latches according to the input requirements for the function of the chip.

The output of the bus and interface synthesizer 907 is input to the logic synthesizer 909, and is output to the logic synthesizer 909.
Also adds the microprocessor core specification 91
0, cache specification 911, digital signal processor (DSP) specification 912, system control and bus specification 9
13, receive input from the graphics subsystem specification 914 and the analog subsystem specification 915. As shown in FIG. 12, the overall system control and control logic for various subsystems (graphics, digital signal processor, analog, etc.)
These corresponding logic circuit descriptions are generated by the logic synthesizer 909. The inputs to the logic synthesizer are the HDL description, the clock and timing specifications from the timing analyzer 916, the circuit library where the control circuit is built and the basic circuit library from the rule database 917. The output of the logic synthesizer 909 is a logic circuit (logic gate) and is stored in the logic circuit database 904. The logic circuits (gates) of the various control logic macros are then placed, routed, and form a layout.

A digital signal processor (DSP) synthesizer 918 generates a data path circuit for the DSP,
These circuits are stored in the logic circuit database 904. Data path circuits are computational elements such as adders, multipliers, shifters, and digital filters. The control logic of the DSP is synthesized using logic synthesis. The data path circuit is then located and routed using a special purpose data path place and route tool 919.

The graphics subsystem specification 914 mainly consists of control logic, custom logic, processors and static RAM (SRAM). The control logic is synthesized. Custom logic is custom layout 9
05, and some circuit parameters, such as device width, are adjusted for performance as needed. The layout is performed by a computer-aided custom layout tool. Graphics processors and specialty SRAMs are custom designed or customized and translated from existing designs such as graphic processor cores and growable SRAM.

Certain functional units, such as microprocessors, SRAM caches, special computing cores, etc., are available in various technologies and in HDL,
It already exists in the logical and layout form, is converted to the technology of the current design by the technology transfer function 920, and is imported into the current design. Most layers of the previous layout can be mapped to corresponding layers of the current technology. Further, the shape of the layout is modified to satisfy the current layout design rules. Those that do not have direct mapping support require special conversions, such as using different metal layers and vias. Transistor device channel lengths are sized for current technology and interconnect sizes and grids are mapped accordingly. The parasitic timing characteristics of the device in the new layout need to be regenerated and the layout and logic / circuit databases need to be updated.

The timing analyzer 916 analyzes the timing of all signals throughout the chip. Find the smallest signal from the chip input to the latch, the smallest signal between the latches, and the smallest signal from the latch output to the chip output. It also looks for the fastest signal that arrives too late at the latch. The timing of these signals is then compared with the timing requirements at the latch and chip I / O. Slack is the difference between the signal arrival time and the time deemed necessary to meet the cycle time requirements. The worst slack is the minimum of all skews. It is an indication of how far a given design is to meet the overall timing requirements. Timing analyzer 916 calculates the R in the wiring to calculate the delay in the device and the overall signal delay.
Analyze timing at the gate or transistor level, including C delay, signal rise and fall times. Resistance, capacitance and RC delay information is RC
It is stored in the timing database 921. These are obtained from the extracted layout and calculated. Clock analyzer 916 performs a similar analysis on the clock signal. Analyze the timing of the clock signal in all latches, including clock wire delay and skew. The results of the timing analyzer are stored in a design database and used at various stages as design parameters to optimize the logical and physical design.

Some custom circuits in the I / O, analog macros and various macros are designed to meet special requirements such as analog devices, layout ground rules, noise decoupling, timing, and area. Requires support custom layout.

The circuit simulation 922 based on the gate and the transistor and the behavior simulation of the HDL description are performed, and the correctness of the logic design is checked by cross-reference.

The test pattern 923 is also generated from the HDL database 903 used for input / output patterns for logic and behavior simulation and hardware test. Specific test patterns for DRAM macros are also generated for logic simulation and testing of DRAM functionality as part of the DRAM configurator 901 and chip compilation process.
An automatic test of the DRAM macro is performed on the logic circuit inside the chip, and the hardware and the integrated DRAM / logic chip are tested.
Testing can be facilitated.

Boolean equivalent tools that do not require input patterns to the design are also logic descriptions (gates and transistors)
And HDL to check for equivalence.

The correctness of the layout is checked by a checking function 924 by comparing the device netlist extracted from the layout with the logic gate and transistor netlist description. The entire layout is also checked for design rule violations by a design rule checker (DRC) tool.

The chip integration tool 925 assembles all the individual components of the chip (various macros, I / O, data and power buses, etc.) and routes them according to chip level wiring and HDL specifications. Integration D
For RAM / logic chips, (1) add decoupling devices along the DRAM and logic power buses and (2) noise decoupling between DRAM macros and logic macros compared to chips without DRAMs (3) separating the DRAM circuit from the switching noise generated by any logic macro (for example, data path) via the power supply bus, and dividing the DRAM and the logic power supply so that these power supply buses Additional steps are performed by not being shared inside the chip but being accessible through some particular point on the chip boundary.

The disclosed method describes a series of steps for compiling the wiring description of a design consisting of DRAM macros and logic macros (either synthetic random logic or custom cores) and any supporting macros into a chip layout.

FIGS. 13 and 14 show eight 8-bits, respectively.
Mb DRAM macro, gate array DRAM control logic, bit block transfer (BitBLT) graphic processor, serial access memory (SA)
M), and other integrated logic / DRAM chips configured with support macros such as phase locked loops (PLLs) and chip I / O drivers, and more specifically, Unified Media Memory (UMM) chips. 2 shows a chip layout structure.

The various logic macros and support macros may be of different design types, such as gate arrays, standard cells, custom designs, analog circuits, etc., to implement various logic functions of the integrated logic / DRAM chip. The layout compiler shown in FIG. 12 takes various macro specifications as input and generates a chip layout.

The present invention provides several DRAM macros, DR
Includes AM controller, computation macro (eg, arithmetic logic unit or ALU), some logic macros such as DRAM buffer, phase locked loop for internal clock generation, built-in automatic test circuit, chip I / O driver, etc. The physical structure of an integrated logic / DRAM chip consisting of various chip support macros is also described. The various logic and support macros can be of very different design styles, such as gate arrays, standard cells, custom designs, analog macros, and the like.

Chip Hardware Description Language (HDL)
Describes the functions, logic and timing specifications of various functional components in the chip, as well as logical components and storage components (DRA).
M, SRAM, cache, etc.), and other elements such as analog (eg, PLL (Phase Locked Loop)), macros, digital-to-analog converters (such as DAC) and I / O components. From the hardware description, each component is further divided, partitioned and each implemented in an optimized physical form of the event. From hierarchical hardware descriptions, chip wiring, macro circuit wiring, chip functionality and correctness to high-level behavior, a mixture of functional simulators, circuit simulators, and analog and analog circuits for performance analysis of critical paths in circuits. Implemented using a simulator. The layout of each macro and all chips is checked for corresponding wiring for layout correctness.

The DRAM components are further divided and reconfigured into several DRAM macros to provide capacity, form,
Requirements such as factors, I / O, banking, degree of parallelism, etc. can be met and are usually implemented in the form of a highly customizable and optimized layout. Computational units, such as fixed and floating point units, signal processing units, etc., are implemented in the form of bit slice based data path custom macros. The performance of these units is critical, and the circuits and transistors are designed to meet important timing requirements. Each control logic unit is typically synthesized by a logic synthesis program as a random logic macro composed of gate arrays or standard cells from the underlying technology's cell library. The control unit supplies various control, address, timing and other signals for the functioning of the chip to other computation and storage units. The high-level description of the chip is generally some custom macros, such as SRAM,
(SRAM) cache and special core, PLL, D
It contains analog circuits such as AC.

The integrated logic / DRAM compiler consists of several programming modules and steps.

1. Functional Partitioning and DRAM Macro Customization and Configuration-From the hardware description of the chip (i.e., HDL), the various functional units are partitioned into physically executable blocks and signal interconnects between blocks. . This step customizes and configures the peripheral control circuits, column and row address decoders and drivers, and I / O circuits for a particular design. As shown in FIGS. 9 and 10, by combining different numbers of DRAM sub-macros (ie, 1 Mb DRAM sub-macros) and reconfiguring the address decoder / driver of the DRAM macro, different sized DRA
M macros can be obtained for specific applications. As shown in FIGS. 9 and 10, by customizing the I / O interface and the driver circuit to the column structure of the DRAM macro, various I / O widths,
For example, X4, X8, X16, X64 can be obtained for a specific application. The driver interface between the logic macro and the DRAM macro includes RC delay and DRAM address and control signals, especially RAS, CA
It is designed to minimize the slew on S, CE. As shown in FIGS. 9 and 10, by customizing the peripheral control circuit of the DRAM macro, various operation modes such as asynchronous and motivation / pipeline can be selected according to a specific application.

2. Macro Placement and Floor Plan Generation-Chip Hardware Description (ie HDL)
Thus, the various functional units are partitioned into physically executable blocks and signal interconnects between the blocks. DRAM macros, logic macros, and various chip support macros are located at different locations on the chip based on this wiring consisting of the signal interconnection information of the functional blocks. Placement objectives are macro size and form factor, input / output (I / O) pin locations within the macro, and power supply partitioning and noise isolation for chip I / O drivers, logic and DRAM, capacitance and I / O width. And minimizing some features of chip-level interconnects, subject to physical constraints and requirements such as DRAM macro distribution, on-chip global bus and clock layout in accordance with US Pat. The entire chip is interconnected according to the location of each chip, and the wiring space between macros is adjusted to minimize the overall chip area. The I / O locations, macro dimensions, and interconnect space dimensions within the chip are parameterized, and the macro allows the interactive execution of location steps and chip-level interconnect steps to minimize chip area and chip constraints. Enable generation of floor plans.

3. Generate Chip Image-This step creates the overall physical layout structure for DRAM macros, logic macros and support macros.
Logic macros consist of a gate array and standard cells or a custom layout. DRAM macros have their own custom layout structure. Each of these logic and DRAM macros has a unique layout of logic and transistor devices, power distribution structures (eg, VDD, GN
D), as well as interconnect requirements for different levels of metal.

4. Generation of power distribution-The overall chip power distribution structure and grid is generated. A power distribution grid inside the logic macro is also generated. Analog macros, such as DRAM macros, logic macros, and PLLs, are laid out in such a way that their individual power distribution networks can be supplied off-chip using independent power supplies. This configuration includes DRAM, logic and analog
It minimizes noise coupling between macros and allows independent testing of logic and DRAM components.

5. Chip-level interconnect generation-All DRAM, logic, and chip support macros are generated according to the chip-level netlist application. On-chip, high bandwidth data, address and control buses connecting DRAM and logic macros are routed in a manner that minimizes RC delay and skew between corresponding equivalent signal points, which are usually Is long and traverses the chip. This involves (1) routing critical signal nets that are wider than the nominal metal width, and (2) balancing wire lengths and topologies from the clock and control signal sources to the various control points (pins) of the various functional units. (3) by adding balanced drivers along the clock and control signal wiring paths.

6. Generating logic macros using gate arrays, standard cells, and custom designs

(6a) This step performs logic synthesis of various logic macros (from hardware description language to logic gates), and then performs mapping to library books or custom circuits determined by technology.

(6b) The book or transistor is then placed and wired according to the basic image requirements of the gate array or standard cell or custom design.

(6c) Wire the clock tree and test scan chain. The layout generated in this step must meet the timing constraints, pin location requirements, and metal utilization requirements specified by the high-level (chip-level) design.

(6d) Layout design rule inspection, timing verification, logic simulation, inspection of layout according to wiring diagram. . . Need to be performed in this step to improve the correctness of the design.

The above steps may need to be repeated to meet timing, physical size, and other requirements imposed on the macro layout.

7. Pin locations, pin properties, macro pin-to-pin timing-this information is extracted from the layout for subsequent chip assembly steps. FIG. 16 shows a layout of a logic macro obtained after layout synthesis, arrangement and wiring.

8. Generation of chip layout-

(8a) After layout of all individual macros (DRAM, logic, support) based on macro pin and timing information, all macros (DRAM,
Logic, support) are wired. Clock interconnects and test scan chains are routed.

(8b) DRAM decoupling elements are added as needed to various parts of the chip. Decoupling elements are separately added to the logic power bus and the DRAM power bus.

(8c) The entire chip is inspected for the correctness and timing of the design rules.

9. Iterative Steps-If some of the chip design requirements were not met, it would be necessary to go back and redo some macro layouts and repeat the macro layout and chip layout generation steps.

FIG. 17 shows an overall flow chart of the integrated logic / DRAM compiler. A DRAM compiler / configurator (block 141) configures the DRAM memory components and generates several DRAM macros.
Information is extracted from the chip-level schematic in function block 140. DRAM, logic block, I / O
And other structural arrangements are determined in function block 142. Chip images for the DRAM, gate array, and custom circuits are created in function block 143. Next, power distribution is determined at function block 144. In this step, the overall chip power distribution structure is created for DRAM macros and logic macros as separate logic and DRAM power distribution networks (including decoupling capacitor structures) inside the chip. Isolating the power distribution network minimizes noise coupling between the DRAM macro and the logic macro via the power bus. Achieving maximum noise immunity between the logic and DRAM components is key to the proper functioning of the integrated logic / DRAM chip. In function block 145, chip-level wiring is determined. In this step, the on-chip logic interface circuit, the logic component and the DRAM
On-chip metal interconnects between components are optimized to achieve maximum system bandwidth and system clock frequency. Steps 142 through 145 constitute top-down floor planning of the chip;
The process is repeated until the wiring, placement, and chip size of all the chips meet the acceptance criteria.

Macro assertions, such as timing, pin locations, metal films, etc., are created in function block 146. Macro synthesis, layout, placement and routing tool functions, DRC and LVS inspection are performed in function block 147. Next, at function block 148, macro layout, timing and pin extraction are performed. Steps 146 to 148 constitute the generation of a macro which is also repeated.

Chip Wiring, Clock, Scan and DR
AM decoupling is performed at function block 149.
Inspection of the chip, inspection of the DRC and LVS, timing, and the like are performed in the function block 150. These two steps constitute the chip assembly part of the method, and if necessary, the loop returns to function block 146 to repeat the macro generation steps of the method until an acceptable chip assembly is generated. . Finally, the layout of the chip is output in the function block 151.

The following is an embodiment of the system on a chip. This is an integrated memory system on a silicon chip for multimedia applications, specifically a Unified Media Memory (UMM) chip. From the UMM hardware description as input and the chip-level block diagram / wiring diagram (FIG. 15), the input is converted to a complete chip layout by a series of computer-aided design (CAD) steps.

FIGS. 13 and 14 show an implementation of the global structure, showing four layers of metal and device
0.25 micron CM with performance enhancements
Integrated logic for Unified Media Memory (UMM) applications designed with OS technology
2 shows a layout of a DRAM chip. 8 UMM chips
It consists of 64 Mb SDRAM arranged in two 8 Mb synchronous DRAM (SDRAM) macros.
SDRAM is 200 MH with 64 I / O width per macro
z, to operate at synchronous single bank R
It supports AS control and 1/2/4/8 / full page burst mode. The eight SDRAM macros are arranged in two global memory banks for interleaving operation and have a wide I / O of 256 bits.
Supply O. The logic functions of the UMM integrated logic / DRAM chip are to provide a 256-bit graphics processor (Bit Block Transfer or BitBLT) for handling graphic data to and from the SDRAM and to export graphic data off the chip. Serial access memory (SAM), a gate array control unit that generates control / timing signals for the overall operation of all macros of the chip, and an off-chip 64 to an on-chip 256-bit data bus It consists of four multiplexers / buffers for high-speed import / export of bit data and a phase locked loop (PLL) for generating an on-chip clock signal synchronized with an external clock. The macro is 133
It communicates through a high bandwidth on-chip 256-bit data bus operating at MHz (up to 200 MHz), an SDRAM address bus, and various control buses such as RAS, CAS, WE, and SDRAM enable. In addition to the external 64-bit data pins, the chip has 32-bit memory address pins, three for graphics functions.
It has a 2-bit serial data output pin, various mode control pins, and a test pin. PowerP
It has an interface to the C (TM) microprocessor bus. The chip can be mounted in a 240 pin package. The basic structure of the gate array random logic macro is also shown in FIG. DRAM macros perform basic memory functions, and together with DRAM macros, logic macro functions perform special functions determined by the overall architecture and logic design.

FIG. 15 shows the floor plan of a UMM chip including the power bus, decoupling capacitor array, chip I / O, DRAM and logic macro layout, and chip level wiring. This chip structure has eight 8MB
DRAM macro, DRAM control logic macro (gate array), Bi for DRAM data computation
tBLT custom processor, serial address
It includes memory (SAM), multiplexers, buffers for communication between the on-chip and off-chip buses, and chip support circuits, PLLs, I / O drivers and pads.

In summary, the following items are disclosed regarding the configuration of the present invention.

(1) Microprocessor core and system logic and dynamic random access memory organized into blocks on a single integrated circuit chip
A computer-implemented method for compiling a layout of a system including a memory (DRAM), extracting information about various functional units from a hardware description database and generating a macro layout and a floor plan of the chip; Configuring the DRAM components and compiling them into DRAM macros, generating an overall physical layout structure of the DRAM macros and logic macros, an overall chip power distribution structure, and power distribution inside the logic macros Generating a grid, including a grid; and generating chip-level interconnections of all DRAM, logic and chip support macros according to a chip-level netlist specification stored in a database. , Generate Implementing a global structure of the chip based on the resulting overall physical layout structure, the generated overall chip power distribution structure and the generated chip-level interconnect, and logic using logic synthesis. After generating the macro, place and route the book of transistors according to the generated chip image, perform clock and timing verification, design rule inspection, and logic simulation,
Checking design correctness, routing interconnects between all macros, generating chip layout by adding decoupling prevention, and rechecking design rules for correctness and timing And outputting the final chip layout for manufacturing processing. (2) The configuration and compilation steps require different amounts of memory capacity, banking and input / output (I / O) bandwidth, different addressing schematics, different modes of operation and time requirements for a particular application. (1) including the step of creating a physical structure, a circuit, and a layout of the embedded growable DRAM macro provided with
A computer implemented method as described in. (3) generating the overall chip power distribution structure for DRAM macros and logic macros separates the logic and DRAM power distribution networks within the chip, thereby providing noise between the DRAM macros and the logic macros by the power bus; • The computer implemented method of (1) above, including the step of minimizing coupling. (4) optimizing on-chip logic interface circuits and on-chip metal interconnects between the logic components and the DRAM components to achieve maximum system bandwidth and system clock frequency. , A computer-implemented method according to (1). (5) A computer for compiling a layout of a system-on-a-chip design including a microprocessor core, and system logic and dynamic random access memory (DRAM) organized in blocks.
A system specification source for a DRAM memory subsystem, microprocessor core, cache, system control bus, and input / output (I / O) tailored to a system-on-a-chip design, and DR
In response to the specification for AM memory subsystem, DRA
DRAM for generating overall physical layout structure of DRAM macro including power distribution network for M macro
In accordance with the configurator and specifications related to the system bus and I / O, various logic and DRA on the chip
A bus and interface synthesizer for synthesizing the logic necessary to connect the M macro, the output of the bus and interface synthesizer, and the specifications for the microprocessor core and cache, are separate from the power distribution network for the DRAM macro. Logic that generates a logic macro and transistor book wiring according to the generated chip image including a power distribution network for the logic macro of the logic macro to minimize noise coupling between the DRAM macro and the logic macro Chip integration that receives the output of the synthesizer and the DRAM configurator, bus and interface synthesizers and logic synthesizers, and routes the interconnections between all macros and creates a chip layout by adding decoupling elements Function. Out extraction function clock and timing verification, perform design rule checking and logic simulation, computer-based design system for checking the correctness of the design. (6) DRAM configurator with different amounts of memory capacity, banking and input / output (I / O) bandwidth, different addressing schematics, different modes of operation and time requirements for specific applications The computer-based design system according to (5), wherein the physical structure, circuit and layout of the buried DRAM macro are created. (7) The chip integration function optimizes on-chip logic interface circuits and on-chip metal interconnects between logic components and DRAM components to achieve maximum system bandwidth and system clock frequency. The computer-based design system according to (5). (8) The computer-based design system according to (5), further including a database of a circuit library accessed by the logic synthesizer. (9) The system specification source includes an analog subsystem specification, and the design system receives the analog subsystem specification, the output from the DRAM configurator, and the logic synthesizer, and provides an output to the chip integration function. • The computer-based design system of (8) above, further comprising a custom layout function that incorporates the subsystem on a chip. (10) The computer-based design according to (8), wherein the system specification source includes a digital signal processor (DSP) specification, and the custom layout specification further receives the DSP specification and incorporates the DSP on a chip. system. (11) The computer-based design system according to (5), further including a clock and timing analyzer that provides an input to the bus and interface synthesizer and the logic synthesizer.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional multichip processor memory system.

FIG. 2 is a block diagram of a single processor memory chip having an on-chip interconnect between a processor and a memory.

FIG. 3 is a block diagram of a conventional system in which a logic chip and a DRAM chip are connected to an external bus.

FIG. 4 is a block diagram of a combinational logic DRAM system on a single chip.

FIG. 5 is a block diagram of a combinational logic DRAM system on a single chip.

FIG. 6 is a block diagram of a combinational logic DRAM system on a single chip.

FIG. 7 is a block diagram of a combinational logic DRAM system on a single chip.

FIG. 8 shows a logic chip and a DRA connected to an external bus.
1 is a block diagram showing a conventional system of M chips and explaining the bandwidth problem of this system.

FIG. 9 is a block diagram of logic and DRAM on a single chip with customized DRAM.

FIG. 10 is a block diagram illustrating a two-dimensionally growable DRAM macro having an n-megabit array and an m-bit I / O path.

FIG. 11 shows a DRAM macro and gate array logic;
Integrated logic / D incorporating custom macro, phase locked loop (PLL), and chip I / O driver
FIG. 2 is a diagram illustrating a chip layout structure of a RAM chip.

FIG. 12 is a block diagram of a system-on-chip design system and compilation according to the present invention.

FIG. 13 illustrates a unified implementation implemented using the present invention.
FIG. 2 is a block diagram of a media memory (UMM).

FIG. 14 is a diagram showing a floor plan of a UMM chip.

FIG. 15 is a schematic diagram of a UMM circuit.

FIG. 16 is a micrograph of a UMM chip layout.

FIG. 17 is a flowchart of layout compilation of an integrated logic / DRAM chip.

[Explanation of symbols]

 21 Processor 22 DRAM 23 On-Chip Interconnection

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/04 V (72) Inventor Way Fun United States 10504 Almon Klong Pond Road, New York 3 (72) Inventor Yasuo Katayama Japan Country 229-11 2130-1-504 Shimokyuzawa, Sagamihara City, Kanagawa Prefecture

Claims (11)

[Claims] 1. A computer implemented compiling system layout including a microprocessor core and system logic and dynamic random access memory (DRAM) organized in blocks on a single integrated circuit chip. Extracting information about the various functional units from a hardware description database and generating a macro layout and floor plan for the chip; configuring the DRAM components of the chip and compiling them into DRAM macros; Generating an overall physical layout structure of the DRAM macro and the logic macro; generating an overall chip power distribution structure and a grid including a power distribution grid inside the logic macro; I have Generating chip-level interconnects for all DRAM, logic and chip support macros according to a multi-level netlist specification; and a generated overall physical layout structure; a generated overall Chip power distribution structure and generated chip
Implementing a global structure of the chip based on the level interconnect; generating logic macros using logic synthesis; then placing and routing a book of transistors according to the generated chip image; Clock and timing verification, design rule inspection,
And perform logic simulation to check the design for correctness, route the interconnections between all macros, generate chip layout by adding decoupling prevention, and correct design rules. And re-examining the timing, and outputting the final chip layout for manufacturing processing. 2. The configuration and compilation steps require different amounts of memory capacity, banking and input / output (I / O) bandwidth, different addressing schematics, different operating modes and times required for a particular application. The computer-implemented method of claim 1, comprising creating a physical structure, circuit, and layout of an embedded growable DRAM macro with requirements. 3. The step of generating an overall chip power distribution structure for DRAM macros and logic macros comprises separating logic and DRAM power distribution networks within the chip, thereby providing a power bus between the DRAM macros and the logic macros. The computer-implemented method of claim 1, comprising the step of minimizing noise coupling of the computer. 4. The method further includes optimizing on-chip logic interface circuits and on-chip metal interconnects between the logic components and the DRAM components to achieve maximum system bandwidth and system clock frequency. The computer-implemented method of claim 1, wherein: 5. A computer-based design system for compiling a layout of a system-on-chip design including a microprocessor core and system logic organized in blocks and dynamic random access memory (DRAM). DRAM memory subsystem, microprocessor core, cache,
Given the system specification source for the system control bus and input / output (I / O) and the specifications for the DRAM memory subsystem,
DRAM including power distribution network for RAM macro
DR to generate the overall physical layout structure of the macro
An AM configurator, a bus and interface synthesizer that receives specifications related to a system bus and I / O, and synthesizes various logics on a chip and logic necessary to connect a DRAM macro, and an output of the bus and interface synthesizer And the specifications for the microprocessor core and cache,
A logic macro and a transistor book wiring are generated in accordance with the generated chip image including a power distribution network for a logic macro different from the power distribution network for the DRAM macro, and a wiring between the DRAM macro and the logic macro is generated. A logic synthesizer that minimizes noise coupling, receives the output of the DRAM configurator, bus and interface synthesizer and logic synthesizer, routes the interconnections between all macros, and adds decoupling elements A chip integration function for generating a chip layout by performing a clock and timing verification, a design rule inspection and a logic simulation to check the correctness of the design. . 6. The DRAM configurator provides different amounts of memory capacity, banking and input / output (I / O) bandwidth, different addressing schematics, different modes of operation and time requirements for a particular application. The computer-based design system of claim 5, wherein the physical structure, circuit and layout of the embedded growable DRAM macro are provided. 7. A chip integration function optimizes on-chip logic interface circuits and on-chip metal interconnects between logic and DRAM components to achieve maximum system bandwidth and system clock frequency. The computer-based design system of claim 5. 8. The computer-based design system of claim 5, further comprising a circuit library database accessed by the logic synthesizer. 9. The system specification source includes an analog subsystem specification, and the design system receives the analog subsystem specification, an output from a DRAM configurator, and a logic synthesizer, and provides an output to a chip integration function. 9. The computer-based design system of claim 8, further comprising a custom layout function that incorporates an analog subsystem on a chip. 10. The computer-based system of claim 8, wherein the system specification source includes a digital signal processor (DSP) specification, and wherein the custom layout specification further receives the DSP specification and embeds the DSP on a chip. Design system. 11. A clock and timing circuit for providing inputs to a bus and interface synthesizer and a logic synthesizer.
The computer-based design system of claim 5, further comprising an analyzer.