KR100578911B1 - Current demultiplexing device and current write type display device using the same - Google Patents

Abstract

In a current write type display device, a demultiplexer is used to transfer a data current to a data line. The demultiplexer is composed of a plurality of sample / hold circuits which are time-divided and sequentially input currents and hold the data lines. The plurality of data lines connected to one demultiplexer are data lines connected to pixels of the same color. In this way, different levels of current may be transmitted in pixels of different colors. In the demultiplexer sample / hold circuit that delivers a large current, a driving transistor having a large ratio of channel width to channel length is used.

Current, Demultiplex, Sample, Hold, Transistor, Saturation Region

Description

CURRENT DEMULTIPLEXING DEVICE AND CURRENT PROGRAMMING DISPLAY DEVICE USING THE SAME}

1 is a schematic diagram of a display device according to an exemplary embodiment of the present invention.

2 is a schematic diagram of a demultiplexer according to an embodiment of the present invention.

3 is a driving timing diagram of the demultiplexer of FIG. 2.

4A to 4D are diagrams illustrating the operation of the demultiplexer of FIG. 2 according to the timing of FIG. 3, respectively.

5 is an equivalent circuit diagram of a sample / hold circuit according to an embodiment of the present invention.

6A and 6B are diagrams showing operating points when sampling the sample / hold circuit of FIG. 5, respectively.

7A and 7B are diagrams showing operating points when holding the sample / hold circuit of FIG. 5, respectively.

FIG. 8 is an equivalent circuit diagram of a sample / hold circuit in which a sampling switching element is p-channel and a holding switching element is n-channel transistor in the sample / hold circuit of FIG. 5.

9 and 10 are diagrams illustrating a relationship between a demultiplexer and a data line of display apparatuses according to the first and second exemplary embodiments of the present invention, respectively.

11 is an equivalent circuit diagram of a circuit in which a sample / hold circuit and a pixel circuit are connected.

12 and 13 are diagrams illustrating operating points during sampling and holding operations of the sample / hold circuit of FIG. 11, respectively.

14 is a schematic diagram of a demultiplexer according to another embodiment of the present invention.

FIG. 15 is a driving timing diagram of the demultiplexer of FIG. 14.

The present invention relates to a current demultiplexing device and a current write type display device using the same, and more particularly, to a demultiplexing device for demultiplexing a current using a sample / hold circuit.

The display device requires a gate driving integrated circuit for driving a scan line and a data driving integrated circuit for driving a data line. In this case, since the data driving integrated circuit converts the digital data signal into an analog signal and applies it to all data lines, the data driving integrated circuit must have an output terminal corresponding to the number of data lines. However, since the number of output terminals of one integrated circuit is limited, many data driving integrated circuits must be used to drive all data lines. Therefore, a method of using a demultiplexer has been proposed to reduce the number of data driving integrated circuits.

For example, a 1: 2 demultiplexer divides and applies a data signal, which is time-divided and applied from a data driver integrated circuit, through two signal lines into two data lines. Therefore, when using a 1: 2 demultiplexer, the number of data driving integrated circuits can be reduced by half. Recently, the liquid crystal display and the organic electroluminescent display have a trend in which the data driving integrated circuit is directly mounted on the panel. In such a case, the number of the data driving integrated circuits needs to be further reduced.

An analog switch is used to configure the demultiplexer. For example, in the case of a 1: 2 demultiplexer, two analog switches are connected between a signal line and two data lines of a data driving integrated circuit, and the analog switches are alternately turned on to be time-divided and applied through the signal lines. Transmit the signal alternately to two data lines. However, in the case of an organic electroluminescent display, there is a method of writing data by using a current as a method of writing data into a pixel. When using an analog switch, a time period in which a data current is applied to one data line is a horizontal period. Half of that. Therefore, compared with the case of not using the demultiplexer, the time for writing data to the pixel is reduced, and thus there is a problem that the data current cannot be sufficiently written to the pixel.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a demultiplexing device and a display device capable of reducing the number of data driving integrated circuits without reducing the time for writing data.

In order to solve this problem, the present invention is to sample / hold only the data current corresponding to the pixel of the same color in one demultiplexer.

According to one aspect of the present invention, a current write type display device including a display area, a data driver, and a demultiplexer is provided. The display area extends in one direction and transmits a first data current representing an image signal, a plurality of scan lines extending in a direction crossing the data lines and transferring a selection signal, and a selection signal from the scanning line. A plurality of pixels for displaying an image by writing a data current from the data line is included. The data driver time-divisionally transfers a second data current corresponding to the first data current through a plurality of signal lines. The demultiplexer includes a plurality of demultiplexers electrically connected to the plurality of signal lines, respectively, and the demultiplexer receives the second data current from the signal line and transfers the first data current to at least two data lines. The demultiplexer includes a plurality of sample / hold circuits, and at least two sample / hold circuits of the plurality of sample / hold circuits sample a current applied through an input terminal, and then output a current corresponding to the sampled current through the output terminal. Output each to at least two data lines. In addition, data lines respectively corresponding to the sample / hold circuits are electrically connected to pixels of the same color.

According to an embodiment of the present invention, the plurality of pixels may include pixels of at least two colors, and at least two data lines corresponding to one demultiplexer may be electrically connected to pixels of one color of at least two colors. .

According to another embodiment of the present invention, the sample / hold circuit stores a sampling switching device that is turned on at the time of sampling, a holding switching device that is turned on at the time of holding, and stores the current applied through the sampling switching device at the time of holding. And a data storage element output through the holding switching element.

According to another embodiment of the present invention, the data storage element of at least one sample / hold circuit of the plurality of sample / hold circuits, the source and the drain are electrically connected to the first power supply and the second power supply, respectively, via a switching element. And a first capacitor electrically connected between the gate and the source of the first transistor, and storing a voltage corresponding to a current applied through the sampling switching element in the first capacitor.

According to another embodiment of the present invention, the maximum value of the current written in the pixel of the first color is greater than the maximum value of the current written in the pixel of the second color, and the first value of the demultiplexer corresponding to the pixel of the first color is defined. the channel width of the first transistor (W ₁₎ and channel length (L ₁₎ ratio (W ₁ / L ₁₎ and a second second channel width of the first transistor of the demultiplexer for the pixels of color (W ₂₎ and the channel length of the It is greater than the ratio (W ₂ / L ₂₎ of the (L _2).

According to another embodiment of the present invention, when the first transistor is a p-channel transistor and the maximum value of the current written in the pixel of the first color is greater than the maximum value of the current written in the pixel of the second color, The voltage of the second power supply of the sample / hold circuit corresponding to the pixel of one color is lower than the voltage of the second power supply of the sample / hold circuit corresponding to the pixel of the second color, or the sample / holding of the pixel of the first color. The voltage of the first power source of the hold circuit may be higher than the voltage of the first power source of the sample / hold circuit corresponding to the pixel of the second color.

According to another embodiment of the present invention, when the first transistor is an n-channel transistor and the maximum value of the current written in the pixel of the first color is greater than the maximum value of the current written in the pixel of the second color, The voltage of the second power supply of the sample / hold circuit corresponding to the pixel of one color is higher than the voltage of the second power supply of the sample / hold circuit corresponding to the pixel of the second color, or the sample / holding voltage corresponding to the pixel of the first color. The voltage of the first power supply of the hold circuit may be lower than the voltage of the first power supply of the sample / hold circuit corresponding to the pixel of the second color.

According to another embodiment of the invention, the sampling switching device, the first switching device electrically connected between the drain and the input terminal of the first transistor, the second switching device for connecting the first transistor in the form of a diode when turned on, And a third switching element electrically connected between the first power supply and the first transistor. The holding switching element may include a fourth switching element electrically connected between the second power supply and the first transistor, and a fifth switching element electrically connected between the first transistor and the output terminal.

According to another embodiment of the invention, the third switching element is a transistor of the same conductivity type as the first transistor, and the fourth switching element is a transistor of the conductivity type opposite to the first transistor.

According to still another embodiment of the present invention, a plurality of sample hold / circuit includes a first and a second in which an input terminal is electrically connected to a signal line, respectively, and an output terminal is electrically connected to one of the at least two data lines, respectively. A sample / hold circuit, and third and fourth sample / hold circuits each having an input terminal electrically connected to the signal line and an output terminal electrically connected to the other one of the at least two data lines, respectively.

According to another embodiment of the present invention, the second and fourth sample / hold circuits are stored through the data line while the first and third sample / hold circuits sample the second data current applied in time division through the signal line. Data stored by the first and third sample / hold circuits through the data line while holding a current corresponding to the data, and while the second and fourth sample / hold circuits sample the second data current applied by being time-divided through the signal line. Hold the current corresponding to.

According to another embodiment of the present invention, the demultiplexer may include a first sample / hold circuit having an input terminal electrically connected to a signal line, an input terminal electrically connected to an output terminal of the first sample / hold circuit, and including at least two data lines. A second sample / hold circuit having an output terminal electrically connected to one data line, a third sample / hold circuit having an input terminal electrically connected to the signal line, and an input terminal electrically connected to an output terminal of the third sample / hold circuit; And a fourth sample / hold circuit having an output terminal electrically connected to the other one of the two data lines.

According to another embodiment of the present invention, while the first and third sample / hold circuits sequentially sample the second data current applied by being time-divided through the signal line, the second and fourth sample / hold circuits perform the data line. Simultaneously holding the sampled current, and sampling the current held by the second and fourth sample / hold circuits while the first and third sample / hold circuits hold the sampling current.

According to another exemplary embodiment of the present invention, the pixel may include a second transistor through which a first data current transmitted through the data line flows, a source of the second transistor, and a gate of the second transistor, and correspond to a current flowing through the second transistor. And a light emitting device that emits light corresponding to a current flowing in the second transistor according to the voltage stored in the second capacitor.

According to another embodiment of the present invention, the light emitting device is a light emitting device using electroluminescence of an organic material.

According to another embodiment of the present invention, the maximum value of the current written in the pixel of the first color is greater than the maximum value of the current written in the pixel of the second color, and corresponds to the pixel of the second transistor. The ratio of the channel width W ₄ and the channel length L ₄ of the second transistor where the ratio W ₃ / L _{4 of the} channel width W ₃ to the channel length L ₄ corresponds to the pixel of the second color It can be higher than (W ₄ / L ₄ ).

According to another embodiment of the present invention, the source of the second transistor is electrically connected to the third power source, the second transistor is a p-channel transistor, and the maximum value of the current written in the pixel of the first color is the second. The voltage of the third power supply that is greater than the maximum value of the current that is written in the pixels of the color may be higher than the voltage of the third power source that corresponds to the pixels of the second color.

According to another embodiment of the present invention, the source of the second transistor is electrically connected to the third power supply, the second transistor is an n-channel transistor, and the maximum value of the current written in the pixel of the first color is the second. The voltage of the third power supply that is greater than the maximum value of the current that is written in the pixels of the color may be lower than the voltage of the third power source that corresponds to the pixels of the second color.

According to another feature of the present invention, a display device including a display area, a demultiplexer, and a data driver is provided. The display area includes a plurality of pixels of a first color arranged in a row direction, a plurality of pixels of a second color respectively formed between two adjacent first color pixels, and a plurality of data lines extending in a column direction. The data line is electrically connected to the pixel of the first color or the pixel of the second color. The demultiplexer includes a plurality of first sample / hold circuit parts and a plurality of second sample / hold circuit parts, wherein the first sample / hold circuit part is electrically connected to a data line corresponding to the pixel of the first color, and the second sample. The / hold circuit portion is electrically connected to the data line corresponding to the pixel of the second color. One output terminal of the data driver is electrically connected to at least two sample / hold circuits of the plurality of first sample / hold circuits and the plurality of second sample / hold circuits through one signal line. In this case, the first sample / hold circuit unit samples the first data current representing the image of the first color applied through the signal line from the data driver, and then outputs a current corresponding to the sampled first data current, and the second sample / hold circuit. The hold circuit unit samples the second data current representing the image of the second color applied through the signal line from the data driver, and then outputs a current corresponding to the sampled second data current.

According to an embodiment of the present invention, the signal line may include at least two of a first signal line and a plurality of second sample / hold circuit parts electrically connected to at least two first sample / hold circuit parts of the plurality of first sample / hold circuit parts. The second signal line may be electrically connected to the second sample / hold circuit.

According to another embodiment of the present invention, the signal line may be electrically connected to at least one of the first sample / hold circuit part and at least one second sample / hold circuit part of the plurality of first sample / hold circuit parts. Is connected.

According to another feature of the invention, there is provided a current demultiplexer device comprising a first sample / hold circuit portion and a second sample / hold circuit portion. The first sample / hold circuit unit includes a plurality of first sample / hold circuits that sample a first current applied through the first signal line and hold a current corresponding to the sampled first current to the first data line. The second sample / hold circuit unit includes a plurality of second sample / hold circuits that sample a second current applied through the second signal line and hold a current corresponding to the sampled second current with the second data line. The first and second sample / hold circuits each include a transistor having a source and a drain electrically connected to the first power supply and the second power supply through a switching element, respectively, and a capacitor electrically connected between the gate and the source of the transistor. The current corresponding to the current applied through the input terminal at the time of sampling flows in the transistor so that the voltage corresponding to the current of the transistor is stored in the capacitor, and the current flows in the transistor corresponding to the voltage stored in the capacitor at the time of holding. At this time, the maximum value of the first current is greater than the maximum value of the second current.

According to one embodiment of the current demultiplexer of the present invention, the ratio W ₁ / L ₁ of the channel width W ₁ and the channel length L ₁ of the transistor of the first sample / hold circuit is equal to the second sample / It may be greater than the ratio W ₂ / L ₂ of the channel width W ₂ and the channel length L ₂ of the transistor of the hold circuit.

According to another embodiment of the invention, the transistor is a p-channel transistor, the voltage of the second power supply of the first sample / hold circuit is lower than the voltage of the second power supply of the second sample / hold circuit, or the first sample / The voltage of the first power supply of the hold circuit may be higher than the voltage of the first power supply of the second sample / hold circuit.

According to another embodiment of the invention, the transistor is an n-channel transistor, the voltage of the second power supply of the first sample / hold circuit is higher than the voltage of the second power supply of the second sample / hold circuit, or the first sample The voltage of the first power supply of the / hold circuit may be lower than the voltage of the first power supply of the second sample / hold circuit.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a directly connected part but also an electrically connected part with another element in between.

Now, a current demultiplexing apparatus and a display device using the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic diagram of a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display area 100, a scan driver 200, a data driver 300, and a demultiplexer 400. In the display area, a plurality of data lines D _{1 to} D _n , a plurality of selected scan lines SE _{1 to} SE _m , a plurality of light emitting scan lines EM _{1 to} EM _m , and a plurality of pixels 110 are formed. The plurality of data lines D _{1 to} D _n extend in the column direction and transmit a data current representing an image to the pixels, and the plurality of selection scan lines SE _{1 to} SE _m and the emission scan lines EM _{1 to} EM _m are provided. It extends in the row direction and transmits a selection signal and a light emission signal to the pixels, respectively. Each pixel is formed in an area defined by two neighboring data lines and two neighboring selection scan lines, and each pixel is formed from one data line D _i in response to a selection signal applied through one selection scan line SE _j . And a display element for displaying a gray scale in response to the data current transmitted from the transistor.

The scan driver 200 sequentially applies a selection signal and a light emission signal to the plurality of selection scan lines SE _{1 to} SE _m and the plurality of light emission scan lines EM _{1 to} EM _m , and the data driver 300 is a demultiplexer. The data current is time-divided at 400 and applied. The demultiplexer 400 applies a data current time-divided from the data driver 300 to the data lines D _{1 to} D _n , and the demultiplexer 400 demultiplexes 1: N. There are n / N signal lines X _{1 to} X _{n / N} transmitting the data current from the data driver 300 to the demultiplexer 400. That is, one signal line X ₁ transfers the time-divided and applied data currents to the N data lines D _{1 to} D _N.

The display area 100 is formed on the insulating substrate, and the scan driver 200 and the demultiplexer 400 are the scan lines SE _{1 to} SE _m and EM _{1 to} EM _m , and the data lines D, respectively, formed on the insulating substrate. _{1 to} D _n ) may be electrically connected. Alternatively, the scan driver 200, the data driver 300, and / or the demultiplexer 400 may be directly mounted on the insulating substrate. In addition, the scan driver 200, the data driver 300, and / or the demultiplexer 400 may scan the scan lines SE _{1 to} SE _m , EM _{1 to} EM _m , the data lines D _{1 to} D _n , and The scan driver 200, the data driver 300, and / or the demultiplexer 400 and the display area 100 may be formed as one panel by forming the same layers as the layers forming the transistor of the pixel.

Hereinafter, the demultiplexer 400 according to an embodiment of the present invention will be described in detail with reference to FIGS. 2, 3, and 4A to 4D. The demultiplexer 400 includes a plurality of demultiplexers, and each demultiplexer corresponds to one signal line X ₁ and N data lines D _{1 to} D _N. In the following description, for convenience, the demultiplexer 400 performs one-to-one demultiplexing, and one demultiplexer corresponds to two data lines.

2 is a schematic diagram of a demultiplexer according to an embodiment of the present invention.

As shown in FIG. 2, a 1: 2 demultiplexer according to an embodiment of the present invention includes four sample / hold circuits 410, 420, 430, and 440. Each sample / hold circuit 410, 420, 430, 440 includes sampling switching elements S1, S2, S3, S4, data storage elements 411, 421, 431, 441 and holding switching elements H1, H2, H3. , H4). The first stages of the sampling switching elements S1, S2, S3, and S4 of the sample / hold circuits 410, 420, 430, and 440 are connected to the data storage elements 411, 421, 431, and 441, respectively. First stages of the elements H1, H2, H3, and H4 are also connected to the data storage elements 411, 421, 431, and 441, respectively. Second stages of the sampling switching elements S1, S2, S3, and S4 of the sample / hold circuits 410, 420, 430, and 440 are commonly connected to the signal line X ₁ . The second ends of the holding switching elements H1 and H3 of the sample / hold circuits 410 and 430 are commonly connected to the data line D ₁ , and the holding switching elements H2 of the sample / hold circuits 420 and 440. , the second stage of the H4) are commonly connected to the data line (D _2). In the following, the terminals connected to the signal lines X _i in the sample / hold circuits 410, 420, 430, and 440 are called input terminals, and the terminals connected to the data lines D ₁ and D ₂ are called output terminals.

Each of the sample / hold circuits 410, 420, 430, and 440 samples currents transmitted through the sampling switching elements S1, S2, S3, and S4 when the sampling switching elements S1, S2, S3, and S4 are turned on. The voltage is stored in the data storage elements 411, 421, 431, and 441 in the form of voltage, and when the holding switching elements H1, H2, H3, and H4 are turned on, the voltages stored in the data storage elements 411, 421, 431, and 441 are turned on. The current corresponding to is held through the holding switching elements H1, H2, H3, and H4.

Here, the recording of the current turned on and input to the data storage device in the form of voltage is defined as 'sampling', and the data stored in the data storage device is defined as 'waiting' and the data recorded in the data storage device. Outputting a current corresponding to is defined as 'holding'.

Next, the operation of the demultiplexer according to the embodiment of the present invention will be described with reference to FIGS. 3 and 4A to 4D.

3 is a timing diagram of a switching element of a demultiplexer according to an exemplary embodiment of the present invention, and FIGS. 4A to 4C are diagrams illustrating the operation of the demultiplexer of FIG. 2 according to the timing of FIG. 3, respectively. In FIG. 3, a low level indicates a state where each switching element is turned on, and a high level indicates a state where each switching element is turned off.

3 and 4A, the sampling switching device S3 and the holding switching devices H1 and H2 are turned on in the T1 section. When the sampling switching device S3 is turned on, the data current applied through the signal line X ₁ is sampled by the storage device 431. When the holding switching elements H1 and H2 are turned on, currents corresponding to data stored in the storage elements 411 and 421 are respectively held by the data lines D ₁ and D ₂ . The sample / hold circuit in which both the sampling switching element S4 and the holding switching element H4 are turned off is in a standby state.

3 and 4B, the sampling switching device S3 is turned off and the sampling switching device S4 is turned on while the holding switching devices H1 and H2 are turned on in the T2 section. Since the holding switching elements H1 and H2 are turned on, currents corresponding to the data stored in the storage elements 411 and 421 are respectively held by the data lines D ₁ and D ₂ . When the sampling switching device S4 is turned on, the data current applied through the signal line X ₁ is sampled by the storage device 441.

3 and 4C, the sampling switching element S4 and the holding switching elements H1 and H2 are turned off and the sampling switching element S1 and the holding switching elements H3 and H4 are turned on in the T3 section. When the sampling switching element S1 is turned on, the data current applied through the signal line X ₁ is sampled by the storage element 411. When the holding switching elements H3 and H4 are turned on, currents corresponding to data stored in the storage elements 431 and 441 are respectively held in the data lines D ₁ and D ₂ in the periods T1 and T2.

Next, referring to FIGS. 3 and 4D, in the period T4, the sampling switching device S1 is turned off and the switching device S2 is turned on while the holding switching devices H3 and H4 are turned on. Since the holding switching elements H3 and H4 are turned on, currents corresponding to the data stored in the storage elements 431 and 441 respectively are held by the data lines D ₁ and D ₂ . When the sampling switching device S2 is turned on, the data current applied through the signal line X ₁ is sampled by the storage device 421.

In this case, the periods T1 and T2 correspond to the periods (hereinafter, referred to as "horizontal periods") in which the pixels connected to the scan lines of one row are turned on by the selection signal, and the periods T3 and T4 correspond to the next horizontal periods. In this manner, the data current can be continuously applied to the data line for one horizontal period, thereby ensuring time for writing data into the pixel. The data current can be transferred to the data line for one frame by repeating the T1 to T4 sections.

Since the four sample / hold circuits included in the demultiplexer of FIG. 2 may be implemented in substantially the same manner, the sample / hold circuit 410 of one of the sample / hold circuits of FIG. This will be described in detail with reference to 7b.

5 is an equivalent circuit diagram of a sample / hold circuit according to an embodiment of the present invention. 6A and 6B are diagrams showing operating points when sampling the sample / hold circuit of FIG. 5, respectively. 7A and 7B are diagrams showing operating points when holding the sample / hold circuit of FIG. 5, respectively.

As shown in FIG. 5, a sample / hold circuit according to an embodiment of the present invention is connected between a signal line X ₁ and a data line D ₁ , and includes a transistor M1, a capacitor Ch, and five switching elements. (Sa, Sb, Sc, Ha, Hb). The parasitic resistance component and the parasitic capacitance component are formed in the data line D _{1. In} FIG. 5, the parasitic resistance components are represented by R1 and R2 and the parasitic capacitance components are represented by C1, C2, and C3. In FIG. 5, the transistor M1 is illustrated as a p-channel type field effect transistor, in particular, a metal oxide semiconductor field-effect transistor (MOSFET).

The switching element Sa is connected between the power supply voltage VDD1 and the source of the transistor M1, and the switching element Ha is connected to the power supply voltage VSS1 and the drain of the transistor M1. Since the transistor M1 is a p-channel type, the power supply voltage VDD1 supplies a voltage higher than the power supply voltage VSS1. Normally, the power supply voltage VDD1 is a positive voltage and the power supply voltage VSS1 is a negative voltage. The switching element Sb is connected between the signal line X ₁ and the gate of the transistor M1, and the switching element Hb is connected between the source of the transistor M1 and the data line D ₁ . The switching element Sc is connected between the signal line X ₁ and the drain of the transistor M1 to connect the transistor M1 in the form of a diode when the switching elements Sb and Sc are turned on. In this case, the switching element Sc may be connected between the gate and the drain of the transistor M1 and may connect the transistor M1 in the form of a diode.

Next, the operation of the sample / hold circuit of FIG. 5 will be described. Here, the switching elements Sa, Sb, Sc are turned on and off at substantially the same timing, and the switching elements Ha, Hb are also turned on and off at the substantially same timing.

First, when the switching elements Sa, Sb and Sc are turned on and the switching elements Ha and Hb are turned off, the transistor M1 is connected in the form of a diode, a current is supplied to the capacitor Ch, and the voltage is charged. The gate potential of the transistor M1 decreases so that a current flows from the source to the drain. When the charge voltage of the capacitor Ch increases with time, and the drain current of the transistor M1 becomes equal to the data current I _DATA from the signal line X ₁ , the charge current of the capacitor Ch is stopped and the capacitor Ch ) Is charged to a constant voltage. That is, the capacitor Ch is charged with the source-gate voltage V _SG of the transistor M1, which is a voltage corresponding to the data current I _DATA from the signal line X ₁ . In this manner, the sample / hold circuit 410 samples the data current I _DATA from the signal line X ₁ .

Next, when the switching elements Sa, Sb and Sc are turned off and the switching elements Ha and Hb are turned on, a current corresponding to the source-gate voltage V _SG charged in the capacitor Ch is switched to the switching element Hb. Is transmitted to the day line D ₁ . In this manner, the sample / hold circuit 410 holds the current with the data line D ₁ .

In the sample / hold circuit 410, all of the switching elements Sa, Sb, Sc, Ha, and Hb are turned off while the sample / hold circuit 420 of FIG. 2 is being sampled (T2). Maintain the charged voltage. That is, the sample / hold circuit 410 is in the standby state.

When the switching elements Sa, Sb, and Sc are turned on, the sample / hold circuit 410 performs a sampling operation, so the switching elements Sa, Sb, and Sc correspond to the sampling switching elements S1 of FIG. When the switching elements Ha and Hb are turned on, the sample / hold circuit 410 performs a holding operation, so the switching elements Ha and Hb correspond to the holding switching elements H1 of FIG. 2. Since the capacitor C1 and the transistor M1 store a voltage corresponding to the data current, the capacitor C1 and the transistor M1 correspond to the data storage element 411.

Accordingly, the switching elements Sa, Sb, and Sc are substantially the same as the timing of the sampling switching element S1, and the switching elements Ha and Hb are substantially the same as the timing of the holding switching element H1. Such timing may vary due to delays in the circuit and the like. In addition, the switching elements Sa, Sb, and Sc may be controlled by one control signal, or may be controlled by different control signals. Similarly, the switching elements Ha and Hb may also be controlled by one control signal and may be controlled by different control signals. In addition, in FIG. 5, the switching elements Sa, Sb, Sc, Ha, and Hb may be implemented as p-channel or n-channel field effect transistors.

In FIG. 5, the sample / hold circuit sources the data current to the signal line X ₁ , that is, the input terminal during the sampling operation, and sinks the data current from the data line D ₁ , that is, the output terminal during the holding operation. Accordingly, the sample / hold circuit shown in FIG. 5 may be used together with the data driver 300 in which the data current is sinked in the signal line X ₁ , that is, the output terminal is in the form of a current sink. In general, the cost of the data driver 300 is reduced because the driving integrated circuit having the output terminal as the current sink is cheaper than the driving integrated circuit having the output terminal as the current source.

In addition, in FIG. 5, when the transistor M1 is implemented as an n-channel field effect transistor and the relative voltage levels of the power supply voltage VDD1 and the power supply voltage VSS1 are changed from each other, the input terminal is a current sink and the output terminal is a current source. Hold circuit can be implemented. Since the structure of the sample / hold circuit can be easily derived from this embodiment by those skilled in the art, description thereof is omitted.

In order to secure a sufficient saturation region in the sampling operation in FIG. 5, the switching element Sa may be formed to have the same conductivity type as the transistor M1. If the switching element Sa is n-channel type unlike the transistor M1 in FIG. 5, the VDD1 voltage is applied to the gate of the switching element Sa during the sampling operation so that the switching element Sa is connected in the form of a diode. do. Accordingly, the characteristic curve between the current and the drain voltage of the transistor M1 according to the source-gate voltage of the transistor M1 is as shown in FIG. 6A. On the contrary, if the switching element Sa is of the p-channel type like the transistor M1, the switching element Sa operates in the linear region during the sampling operation, and the characteristic curve is as shown in Fig. 6B. 6A and 6B, it can be seen that the voltage range of the operating point that can be used at the same current in FIG. 6B is wider than that in FIG. 6A.

Similarly, in FIG. 5, in order to secure a sufficient saturation region in the holding operation, the switching element Ha may be formed in a conductive type opposite to the transistor M1. If the switching element Ha is a p-channel type like the transistor M1 in FIG. 5, the VSS1 voltage is applied to the gate of the switching element Ha during the holding operation so that the switching element Ha is connected in the form of a diode. do. Accordingly, the characteristic curve between the current and the source voltage of the transistor M1 according to the gate-source voltage of the transistor M1 becomes as shown in FIG. 7A. On the contrary, if the switching element Ha is an n-channel type, the switching element Ha operates in the linear region during the holding operation, so that the characteristic curve is as shown in Fig. 7B. In FIGS. 7A and 7B, the voltage VDD2 is a power supply voltage to which the data line D ₁ is connected through the pixel when held. 7A and 7B, it can be seen that the voltage range of the operating point that can be used at the same current in FIG. 7B is wider than that in FIG. 7A.

In the case where the switching elements Sa and Ha are formed in p-channel and n-channel types, respectively, the switching elements Sb and Sc turned on during the sampling operation to control sampling and holding as one control signal are p. The switching element Hb formed of the channel transistor and turned on in the holding operation may be formed of the n-channel transistor. FIG. 8 is a sample / hold circuit in which the switching elements Sa, Sb, and Sc are formed of p-channel transistors and the switching elements Ha and Hb are formed of n-channel transistors in the sample / hold circuit of FIG. 5. 8, the switching elements Sa, Sb and Sc are controlled by the control signal A and the switching elements Ha and Hb are controlled by the control signal B. As shown in FIG.

Next, a display device including a demultiplexer using a sample / hold circuit will be described with reference to FIGS. 9 and 10.

9 and 10 are diagrams illustrating a relationship between a demultiplexer and a data line of display apparatuses according to the first and second exemplary embodiments of the present invention, respectively.

In FIGS. 9 and 10, red, green, and blue pixels are alternately arranged in the row direction, and pixels of the same color are arranged in the column direction. Data lines connected to red, green, and blue pixels, respectively, are represented by R _i , G _i , and B _i . 9 and 10, for convenience, it is assumed that there are two red, green, and blue pixels in the row direction, and more than two pixels are connected in the same pattern as shown in FIGS. 9 and 10.

9, in the demultiplexer 400 of the display device according to the first exemplary embodiment, an output terminal of the demultiplexer 401 having an input terminal connected to a signal line X ₁ is a data line R ₁ , G _1. ) it is coupled to, the input end is connected to the signal line (X ₂₎ the data lines (B _1, R _1), the output terminal of the demultiplexer 402 is coupled to demultiplexer (403 is the input terminal connected to the signal line (X ₃₎ ) Is connected to the data lines R ₁ and G ₁ . The sampling switching elements S1, S2, S3, S4 of each demultiplexer 401, 402, 403 are controlled by separate signal lines, and the holding switching elements H1, H2 are controlled by a common signal line. Holding switching elements H3 and H4 are also controlled by a common signal line.

However, in general, since the current range required for expressing gray scales is different in each of the red, green, and blue pixels, the operating voltage range of the current of one output terminal in the data driver 300 corresponds to the current range corresponding to one color. If set to, the current corresponding to a pixel of a different color may not be output normally in the corresponding operating voltage range. Accordingly, when two colors of pixels are connected to one output terminal as shown in FIG. 9, an appropriate gray level may not be expressed in one colors of pixels. Accordingly, as shown in FIG. 10, each signal line X _i of the data driver 300 is preferably assigned to pixels of the same color through the demultiplexer.

Referring to FIG. 10, in the demultiplexer 400 of the display device according to the second exemplary embodiment, an output terminal of the demultiplexer 401 whose input terminal is connected to the signal line X ₁ is an R pixel data line R. ₁ , R ₂ , and the output terminal of the demultiplexer 402, whose input is connected to the signal line (X ₂ ), is connected to the data lines (G ₁ , G ₂ ) of the G pixel, and the input terminal is the signal line (X ₃ ). An output terminal of the demultiplexer 403 connected to is connected to the data lines B ₁ and B ₂ of the B pixel. That is, each demultiplexer is connected to data lines of pixels of the same color.

In this case, since each signal line X _j of the data driver 300 transmits only data currents corresponding to pixels of the same color, red, green, and blue pixels may have respective current ranges.

9 and 10, the sample / hold circuit part including two sample / hold circuits 410 and 430 and the sample / hold circuit part including two sample / hold circuits 420 and 440 each have one color. Corresponds only to the pixel. However, since the luminous efficiency and the current range used are different according to the color, the pixel / sample circuit suitable for the pixel of each color can be designed as shown in FIGS. 9 and 10. Hereinafter, a case in which the pixel circuit of FIG. 11 is formed in the pixels of the display device of FIGS. 9 and 10 will be described with reference to FIGS. 12 and 13 with reference to the sample / hold circuit.

11 is an equivalent circuit diagram of a circuit in which a sample / hold circuit and a pixel circuit are connected. 12 and 13 are diagrams illustrating operating points during sampling and holding operations of the sample / hold circuit of FIG. 11, respectively.

First, referring to FIG. 11, the pixel circuit 110 is connected to the data line D ₁ of the sample / hold circuit of FIG. 8. The pixel circuit 110 of FIG. 11 is a pixel circuit in which data is written by electric current and uses electroluminescence of an organic material. The pixel circuit 110 includes four transistors P1, P2, P3, and P4, a capacitor Cst, and a light emitting device OLED. In FIG. 11, the transistors P1, P2, P3, and P4 are illustrated as p-channel field effect transistors.

The source of the transistor P1 is connected to the power supply voltage VDD2, and the capacitor Cst is connected between the source and the gate of the transistor P1. Transistor (P2) is responsive to the selection signal from the data line (D _i) and the transistor (P1) connected between the gate and the selection scan line (SE ₁₎ a. The transistor P3 is connected between the drain of the transistor P1 and the data line D ₁ and connects the transistor P1 in the form of a diode with the transistor P2 in response to a selection signal from the selection scan line SE ₁ . do. The transistor P4 is connected between the drain of the transistor P1 and the light emitting element OLED and transmits a current from the transistor P1 to the light emitting element OLED in response to a light emission signal from the light emitting scan line EM ₁ . . The cathode of the light emitting element OLED is connected to a power supply voltage VSS3 lower than the power supply voltage VDD2.

At this time, when the transistors P2 and P3 are turned on by the selection signal from the selection scan line SE ₁ , the current from the data line D ₁ flows into the drain of the transistor P1, and the transistor P1 corresponding to this current is turned on. Source-gate voltage is stored in the capacitor Cst. When the light emission signal is applied from the light emitting scan line EM ₁ , the transistor P4 is turned on so that the current I _OLED of the transistor P1 corresponding to the voltage stored in the capacitor Cst is supplied to the light emitting device OLED. . According to this current, the light emitting element emits light.

Next, as illustrated in FIG. 11, the operation point of the sample / hold circuit when the pixel circuit is connected to the sample / hold circuit through the data line will be described.

First, as described above, the characteristic curves between the current and the drain voltage of the transistor M1 according to the source-gate voltage of the transistor M1 at the time of sampling are as shown in ①, ②, ③ and ④ of FIG. At this time, each characteristic curve ①, ②, ③, ④ corresponds to a different source-gate voltage of the transistor M1. The curves L1 and L2 represent the relationship between the current flowing through the transistors Sa and M1 and the voltage drop through the transistors Sa and M1, respectively, by fixing the source voltage to the power supply voltage VDD1. In addition, since the transistors Sa and Sc all have a large source-gate voltage and operate in a linear region, the voltage drops through the transistors Sa and Sc are equal to each other. Accordingly, the voltage drop curve of the transistor Sb is also equal to the curve ( It is displayed almost the same as L1).

The voltage of the node N1 is a voltage drop across the transistors Sa, M1, and Sc from the power supply voltage VDD1, and the current flowing through these transistors Sa, M1, and Sc and these transistors Sa, M1. , And the relationship between the voltage drop through (Sc) becomes as curve L3. Therefore, curve L3 is equal to twice the distance between curve L1 and power supply voltage VDD1 at any current value and the sum of the distance between curve L2 and power supply voltage VDD1 at power supply voltage VDD1. Subtracted form. That is, as shown in FIG. 12, the curve L3 has a form in which the curve L2 is inclined to the left. The operating point at the time of sampling is determined at the intersection of the curve L3 and the characteristic curve L4 between the current and the voltage at the output terminal of the data driver 300. The current at the output of the data driver 300 has a substantially constant value over a range of operating voltage ranges, as shown by curve L4. As illustrated in FIG. 12, when a current corresponding to I _DATA is output from an output terminal of the data driver 300, an operating point is determined at P.

When the operating point is determined to be P, the source-gate voltage corresponding to the curve ② passing through the operating point P is stored in the capacitor Cst, and the operating point P is in the saturation region of the curve ②. .

Next, the characteristic curves between the current and the source voltage of the transistor M1 according to the source-gate voltage of the transistor M1 during the holding operation are shown as V, V, V and V in FIG. 13, respectively. The source-gate voltage at (V, V, V, V) corresponds to the source-gate voltage in the curves 1, 2, 3 and 4 of FIG. Therefore, the characteristic curve between the current and the source voltage of the transistor M1 follows the curve when held in accordance with the operating point P determined at the time of sampling.

Curve in Figure 13 (L5) is a transistor (Hb) and the data line (D ₁₎ a through current to flow and accordingly transistor (Hb) and the data line data line the relationship between the voltage drop through the (D ₁₎ (D ₁ And the voltage at the connection point between the pixel circuit 110 and the pixel circuit 110 are fixed to the power supply voltage VDD2. As in FIG. 12, the voltage drop through the transistors P1 and P3 is added to the curve L5 to flow through the transistors P1 and P3, the data line D ₁ , and the transistor Hb from the power supply voltage VDD2. A curve L6 representing the relationship between the current and the voltage at the node N2 as the source of the transistor M1 can be obtained. Since the current of the curve L6 and the current flowing in the transistor M1 are the same, the operating point Q at the time of holding is determined at the intersection of the curve L6 and the characteristic curve of the transistor M1.

In addition, the characteristic curves ⑪, ⑫, ⑬, 13 of FIG. 13 actually form the sum of the voltage drop in the transistor Ha after the characteristic curves ①, ②, ③, and ④ of FIG. 12 are symmetrically moved. Therefore, when holding after sampling, the operating point P is the same as moving along the curve ②. That is, it can be said that the source-drain voltage of the transistor M1 changes during holding after sampling.

However, as shown in FIGS. 12 and 13, the current in the saturation region in the actual characteristic curve is not constant but increases in accordance with the voltage, and the slope of the current varies according to the characteristic distribution of the transistor M1. The current I _D of the transistor M1 in the saturation region may be approximated by Equation 1 below.

Where μ is the carrier mobility, C _ox is the oxide capacitance, V _SG is the source-gate voltage, V _TH is the threshold voltage, λ is the constant, and V _SD is the source-drain voltage.

Therefore, even when the same current is sampled, the current at holding depends on the characteristics of the transistor M1, and this deviation is represented by the ratio of the channel width W and the channel length L of the transistor M1 ( The larger the W / L), the larger. Therefore, as the ratio (W / L) of the channel width (W) and the channel length (L) of the transistor (M1) is reduced, the variation of the holding current according to the characteristic variation of the transistor (M1) can be reduced.

In the case of using the pixel using the electroluminescence of the organic material as illustrated in FIG. 11, the light emission efficiency of the organic material displaying green is 3 to 4 greater than that of the organic material displaying blue. Since it is about twice as high, it is necessary to make the variation of the holding current applied to the green pixel particularly small. That is, it is necessary to minimize the ratio W / L of the channel width W and the channel length L of the transistor M1 of the sample / hold circuit connected to the data line of the green pixel having the highest luminous efficiency. .

In addition, when the ratio W / L of the channel width W and the channel length L of the transistor M1 is small, the slope of the curve L3 in FIG. 12 becomes small, and thus moves in accordance with the data current I _DATA . The voltage range of the operating point P becomes wider. However, since the current range used for the pixel of the blue organic material is about 2.5 times the current range used for the pixel of the green organic material due to the nature of the organic material, the blue organic material is applied to the sample / hold circuit optimized for the pixel of the green organic material. When used in a pixel of, the operating point P may be outside the operating voltage region of the output terminal of the data driver 300 illustrated in FIG. 12.

Therefore, in a sample / hold circuit applied to a pixel of a blue organic material having a large data current range, the power supply voltage VDD1 is increased or the ratio of the channel width W and the channel length L of the transistor M1 (W / L) is increased. It is necessary to enlarge). When the power supply voltage VDD1 increases, the curve is moved to the right as a whole in FIG. 12, so that the operating point P can enlarge the moving range. However, this also increases the minimum value of the data current that can be handled, thereby limiting the adjustment range and increasing power consumption. Also, the cost increases because a different power source must be used in the sample / hold circuit applied to the blue pixel. In addition, when the ratio W / L of the channel width W and the channel length L is increased, the voltage range in which the operating point P is formed is narrowed, and thus the operating point within the operating voltage range of the output terminal of the data driver 300 is reduced. P) can be formed. In this case, however, the variation of the holding current may increase as shown in Equation 1. Therefore, you can use a combination of the two conditions described above.

Next, even during holding, the operating point Q should be set in the saturation region of the characteristic curve of the transistor M1 for all data current ranges. In addition, since the variation in the holding current applied to the green pixel having high luminous efficiency needs to be particularly small, the channel width W and the channel length L of the transistor M1 of the sample / hold circuit connected to the data line of the green pixel are small. It is necessary to minimize the ratio (W / L).

In addition, when the ratio W / L of the channel width W and the channel length L of the transistor M1 is small, the operating point Q is the transistor in the sample / hold circuit connected to the blue pixel having a large range of data currents. It may be outside the saturation region of the characteristic curve of M1. To solve this problem, a method of increasing the ratio W / L of the channel width W and the channel length L of the transistor M1, a method of lowering the power supply voltage VSS1, and a method of increasing the power supply voltage VDD2 is provided. Alternatively, there is a method of increasing the ratio W / L of the channel width W and the channel length L of the transistor P1.

First, in FIG. 13, the slope of the linear region is large when the ratio W / L of the channel width W and the channel length L of the transistor M1 is large, and the ratio W / L of the channel width and the channel length is large. Since the smaller the smaller, the transistor M1 having a large ratio W / L of the channel width W and the channel length L can move the starting point of the saturation region to the left.

Second, when the power supply voltage VSS1 is lowered, since the starting point of the characteristic curve of the transistor M1 moves to the left in FIG. 13, the starting point of the saturation region may move to the left. As such, when the start point of the saturation region moves to the left, the range of the saturation region in which the operating point Q can move is increased.

Third, since the vertex of the curve L6 moves to the right when the power supply voltage VDD2 increases, the operating point Q is formed to move to the right, so that the operating point Q may move in the saturation region.

Fourth, since the slope of the curve E increases in the ratio W / L of the channel width W and the channel length L of the transistor P1, the operating point Q is moved to the right, thereby operating point Q ) Can be moved within the saturation region.

In summary, in the sample / hold circuit of the demultiplexer connected to the pixel of the color using the large data current, the ratio of the channel width (W) to the channel length (L) (W / L) Using a large transistor M1, using a low power supply voltage VSS1, or using a high power supply voltage VDD1, VDD2, or the ratio of channel width (W) to channel length (L) in a pixel (W / L) The transistor P1 having a large value may be used.

The above-described condition is a condition established when the transistor M1 is a p-channel type, and a demultiplexer connected to a pixel of a color using a large data current when the transistors M1 and P1 are n-channel type. In the sample / hold circuit, the high power supply voltage VSS1 or the low power supply voltages VDD1 and VDD2 may be used.

As described above, the embodiment of the present invention has been described with reference to the demultiplexer connected to the sample / hold circuit as shown in FIG. 2, but the present invention is not limited thereto and may be applied to the demultiplexer connected to the sample / hold circuit in another form. .

For example, as shown in FIG. 14, the sample / hold circuits 410 and 430 may be connected in series and the sample / hold circuits 420 and 440 may be connected in series in a 1: 2 demultiplexer. Referring to FIG. 15, the sample / hold circuit 410 samples the current applied through the signal line X _i during the T11 period, and the sample / hold circuits 430 and 440 respectively represent the data lines D ₁ and D ₂ . Hold the current through. In the period T12, the sample / hold circuit 420 samples the current applied through the signal line X _i , and the sample / hold circuits 430 and 440 hold the current through the data lines D ₁ and D ₂ , respectively. do. In the period T13, the sample / hold circuits 410 and 420 hold a current, and the sample / hold circuits 430 and 440 sample the stored current to store data. The T11, T12, and T13 periods correspond to one horizontal period, and the T11, T12, and T13 periods are repeated to perform the demultiplexing operation.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, different current levels may be used for pixels of different colors. In a demultiplexer using a high level current, sufficient saturation region can be obtained. In addition, the use of a sample / hold circuit can reduce the number of data driving integrated circuits without reducing the data write time.

Claims (38)

A plurality of data lines extending in one direction and transmitting a first data current representing an image signal, a plurality of scanning lines extending in a direction crossing the data lines and transferring a selection signal, and in response to a selection signal from the scanning lines; A display area including a plurality of pixels for writing an image of data from a data line and displaying an image; A data driver for time-dividing and transferring a second data current corresponding to the first data current through a plurality of signal lines; and A demultiplexer electrically connected to the plurality of signal lines, the demultiplexer having a plurality of demultiplexers for receiving the second data current from the signal line and transferring the first data current to at least two data lines; The demultiplexer includes a plurality of sample / hold circuits, and at least two sample / hold circuits of the plurality of sample / hold circuits output current corresponding to the sampled current after sampling a current applied through an input terminal. Respectively output to the at least two data lines through And a data line corresponding to each of the sample / hold circuits is electrically connected to pixels of the same color. The method of claim 1, The plurality of pixels includes pixels of at least two colors, And the at least two data lines corresponding to one demultiplexer are electrically connected to one of the pixels of at least two colors. The method of claim 2, The sample / hold circuit is, A sampling switching element turned on at the time of sampling, A holding switching element which is turned on during holding, and And a data storage element for storing a current applied through the sampling switching element at the time of sampling and outputting the current through the holding switching element at the time of holding. The method of claim 3, The data storage element of at least one sample / hold circuit of the plurality of sample / hold circuits may include: A first transistor having a source and a drain electrically connected to the first power supply and the second power supply through a switching element, and a first capacitor electrically connected between the gate and the source of the first transistor, And a voltage corresponding to a current applied through the sampling switching element in the first capacitor. The method of claim 4, wherein A maximum value of a current written in a pixel of a first color among the at least two colors of pixels is greater than a maximum value of a current written in a pixel of a second color among the pixels of at least two colors, The ratio W ₁ / L ₁ of the channel width W ₁ to the channel length L ₁ of the first transistor of the sample / hold circuit corresponding to the pixel of the first color is applied to the pixel of the second color. And a channel width (W ₂ ) and channel length (L ₂ ) of the first transistor of the demultiplexer corresponding to the ratio (W ₂ / L ₂ ). The method of claim 4, wherein The first transistor is a p-channel transistor, and the maximum value of the current written in the pixel of the first color among the at least two colors of pixels is the maximum value of the current written in the pixel of the second color among the pixels of the at least two colors. Greater than The current write type display device wherein the voltage of the second power supply of the sample / hold circuit corresponding to the pixel of the first color is lower than the voltage of the second power supply of the sample / hold circuit corresponding to the pixel of the second color. . The method of claim 4, wherein The first transistor is an n-channel transistor, and a maximum value of a current written in a pixel of a first color among the pixels of at least two colors is a maximum value of a current written in a pixel of a second color among the pixels of the at least two colors. Greater than The current write type display device in which the voltage of the second power supply of the sample / hold circuit corresponding to the pixel of the first color is higher than the voltage of the second power supply of the sample / hold circuit corresponding to the pixel of the second color. . The method of claim 4, wherein The first transistor is a p-channel transistor, and the maximum value of the current written in the pixel of the first color among the at least two colors of pixels is the maximum value of the current written in the pixel of the second color among the pixels of the at least two colors. Greater than The current write type display device in which the voltage of the first power supply of the sample / hold circuit corresponding to the pixel of the first color is higher than the voltage of the first power supply of the sample / hold circuit corresponding to the pixel of the second color. . The method of claim 4, wherein The first transistor is an n-channel transistor, and a maximum value of a current written in a pixel of a first color among the pixels of at least two colors is a maximum value of a current written in a pixel of a second color among the pixels of the at least two colors. Greater than The current write type display device, wherein the voltage of the first power supply of the sample / hold circuit corresponding to the pixel of the first color is lower than the voltage of the first power supply of the sample / hold circuit corresponding to the pixel of the second color. . The method according to any one of claims 4 to 9, The sampling switching device may include a first switching device electrically connected between the drain of the first transistor and the input terminal, a second switching device connecting the first transistor in a diode form at turn-on, and the first power supply; A third switching element electrically connected between the first transistor, The holding switching element may include a fourth switching element electrically connected between the second power supply and the first transistor, and a fifth switching element electrically connected between the first transistor and the output terminal. Device. The method of claim 10, And the third switching element is a transistor of the same conductivity type as the first transistor, and the fourth switching element is a conductivity type transistor opposite to the first transistor. The method according to any one of claims 1 to 9, The demultiplexer, First and second sample / hold circuits each having an input terminal electrically connected to the signal line and an output terminal electrically connected to one of the at least two data lines; and And a third and fourth sample / hold circuits each having an input terminal electrically connected to the signal line and an output terminal electrically connected to the other one of the at least two data lines. The method of claim 12, The second and fourth sample / hold circuits correspond to data stored through the data lines while the first and third sample / hold circuits sample the second data current that is time-divisionally applied through the signal lines. Holding current, The first and third sample / hold circuits correspond to data stored through the data lines, while the second and fourth sample / hold circuits sample the second data current that is time-divisionally applied through the signal lines. A current write type display device for holding a current. The method according to any one of claims 1 to 9, The demultiplexer, A first sample / hold circuit having an input terminal electrically connected to the signal line; A second sample / hold circuit having an input terminal electrically connected to an output terminal of the first sample / hold circuit and an output terminal electrically connected to one of the at least two data lines; A third sample / hold circuit having an input terminal electrically connected to the signal line, and And a fourth sample / hold circuit having an input terminal electrically connected to an output terminal of the third sample / hold circuit and an output terminal electrically connected to another data line of the at least two data lines. The method of claim 14, Currents sampled by the second and fourth sample / hold circuits through the data line, while the first and third sample / hold circuits sequentially sample the second data current that is time-divisionally applied through the signal line. Holding at the same time, And the second and fourth sample / hold circuits sample the held current while the first and third sample / hold circuits hold a sampling current. The method according to any one of claims 1 to 9, Each of the at least two colors of pixels, A second transistor through which the first data current is transmitted through the data line, A second capacitor electrically connected between the source and the gate of the second transistor and storing a voltage corresponding to a current flowing in the second transistor, and And a light emitting device that emits light in response to a current flowing through the second transistor according to a voltage stored in the second capacitor. The method of claim 16, And the light emitting element is a light emitting element using electroluminescence of an organic material. The method of claim 16, A maximum value of a current written in a pixel of a first color among the at least two colors of pixels is greater than a maximum value of a current written in a pixel of a second color among the pixels of at least two colors, The second transistor whose ratio W ₃ / L ₄ of the channel width W ₃ and the channel length L ₄ of the second transistor corresponding to the pixel of the first color corresponds to the pixel of the second color A current write-type display device having a channel width (W ₄ ) of and a ratio (W ₄ / L ₄ ) of the channel length (L ₄ ) of a larger than. The method of claim 16, A source of the second transistor is electrically connected to a third power source, the second transistor is a p-channel transistor, and a maximum value of a current written in a pixel of a first color among the pixels of at least two colors is at least two; Is greater than the maximum value of the current written in the pixel of the second color of the color pixel, And a voltage of the third power supply corresponding to the pixel of the first color is higher than a voltage of the third power supply corresponding to the pixel of the second color. The method of claim 16, A source of the second transistor is electrically connected to a third power source, the second transistor is an n-channel transistor, and a maximum value of a current written in a pixel of a first color among the pixels of the at least two colors is at least two; Is greater than the maximum value of the current written in the pixel of the second color among the pixels of the color, And a voltage of the third power source corresponding to the pixel of the first color is lower than a voltage of the third power source corresponding to the pixel of the second color. Pixels of a plurality of first colors arranged in a row direction, pixels of a plurality of second colors respectively formed between the two adjacent first color pixels, and pixels of the plurality of first or second colors extending in a column direction A display area including a plurality of data lines each electrically connected to the display device; A plurality of first sample / hold circuits electrically connected to data lines corresponding to the pixels of the first color, and a plurality of second samples / holds electrically connected to data lines corresponding to the pixels of the second color, respectively. A demultiplexer including a circuit portion, and One output terminal includes a data driver electrically connected to at least two sample / hold circuit parts of the plurality of first sample / hold circuit parts and the plurality of second sample / hold circuit parts, respectively, through one signal line. The first sample / hold circuit unit samples a first data current representing the image of the first color applied through the signal line from the data driver, and then outputs a current corresponding to the sampled first data current. The second sample / hold circuit unit writes a current for outputting a current corresponding to the sampled second data current after sampling a second data current representing the image of the second color applied through the signal line from the data driver. Type display device. The method of claim 21, The signal line may include a first signal line electrically connected to at least two first sample / hold circuit units of the plurality of first sample / hold circuit units, and at least two second sample / hold circuit units of the plurality of second sample / hold circuit units. And a second signal line electrically connected to the current write type display device. The method of claim 21, The signal line is a current write type electrically connected to at least one first sample / hold circuit part of the plurality of first sample / hold circuit parts and at least one second sample / hold circuit part of the plurality of second sample / hold circuit parts. Display device. The method of claim 21, The first and second sample / hold circuits, respectively, First and second sample / hold circuits having an input terminal coupled to the signal line and an output terminal coupled to the data line; And the second sample / hold circuit holds while the first sample / hold circuit is sampling, and the first sample / hold circuit holds while the second sample / hold circuit is sampling. The method of claim 21, The first and second sample / hold circuits, respectively, A first sample / hold circuit having an input connected to the signal line; A second sample / hold circuit having an input terminal connected to an output terminal of the first sample / hold circuit and an output terminal connected to the data line; The first sample / hold circuit samples the data applied through the signal line, and the second sample / hold circuit samples the current held by the first sample / hold circuit to obtain a current corresponding to the sampled current. And a current write type holding device holding the data line. The method of claim 24 or 25, At least one of the first and second sample / hold circuits, A sampling switching device connected to the input terminal and turned on during sampling, a holding switching device connected to the output terminal and turned on during holding, and a data storage device connected between the sampling switching device and the holding switching device, The data storage device includes a transistor having a source and a drain electrically connected to a first power supply and a second power supply through a switching element, and a capacitor connected between the gate and the source of the transistor, When sampling, a current flows in the transistor so that a voltage corresponding to a current applied through the sampling switching element is stored in the capacitor, and a current of the transistor corresponds to a voltage stored in the capacitor during holding. A current writing type display device flowing through the. The method of claim 26, The maximum value of the first data current is greater than the maximum value of the second data current, The ratio W ₁ / L ₁ of the channel width W ₁ to the channel length L ₁ of the transistor of the first sample / hold circuit part is the channel width W ₂ of the transistor of the second sample / hold circuit part. ) And the current write type display device having a larger than the ratio (W ₂ / L ₂ ) of the channel length (L ₂ ). The method of claim 26, The transistor is a p-channel transistor, the maximum value of the first data current is greater than the maximum value of the second data current, And a voltage of the second power supply of the first sample / hold circuit portion is lower than a voltage of the second power supply of the sample / hold circuit portion. The method of claim 26, The transistor is an n-channel transistor, the maximum value of the first data current is greater than the maximum value of the second data current, And a voltage of the second power supply of the first sample / hold circuit part is higher than a voltage of the second power supply of the second sample / hold circuit part. The method of claim 26, The transistor is a p-channel transistor, the maximum value of the first data current is greater than the maximum value of the second data current, And a voltage of the first power supply of the first sample / hold circuit part is higher than a voltage of the first power supply of the sample / hold circuit part. The method of claim 26, The transistor is an n-channel transistor, the maximum value of the first data current is greater than the maximum value of the second data current, And a voltage of the first power supply of the first sample / hold circuit part is lower than a voltage of the first power supply of the second sample / hold circuit part. A first sample / hold circuit unit including a plurality of first sample / hold circuits for sampling a first current applied through a first signal line and holding a current corresponding to the sampled first current with a first data line; and And a second sample / hold circuit section including a plurality of second sample / hold circuits for sampling a second current applied through a second signal line and holding a current corresponding to the sampled second current to a second data line. , The first and second sample / hold circuits, respectively, A transistor having a source and a drain electrically connected to the first power supply and the second power supply through a switching element, and a capacitor connected between the gate and the source of the transistor, respectively, and corresponding to a current applied through an input terminal during sampling; The current flows through the transistor so that a voltage corresponding to the current of the transistor is stored in the capacitor, and the current of the transistor flows to the output terminal in response to the voltage stored in the capacitor. The maximum value of the first current is greater than the maximum value of the second current, and the ratio W ₁ / L ₁ of the channel width W ₁ and the channel length L ₁ of the transistor of the first sample / hold circuit. ) Is greater than the ratio (W ₂ / L ₂ ) of the channel width (W ₂ ) and channel length (L ₂ ) of the transistor of the second sample / hold circuit. A first sample / hold circuit unit including a plurality of first sample / hold circuits for sampling a first current applied through a first signal line and holding a current corresponding to the sampled first current with a first data line; and And a second sample / hold circuit section including a plurality of second sample / hold circuits for sampling a second current applied through a second signal line and holding a current corresponding to the sampled second current to a second data line. , The first and second sample / hold circuits, respectively, A transistor having a source and a drain electrically connected to the first power supply and the second power supply through a switching element, and a capacitor connected between the gate and the source of the transistor, respectively, and corresponding to a current applied through an input terminal during sampling; A current corresponding to the transistor is stored in the capacitor, a voltage corresponding to the current of the transistor is stored in the capacitor, and a current of the transistor corresponding to the voltage stored in the capacitor flows to an output terminal during holding. The maximum value of the first current is greater than the maximum value of the second current, the magnitude of the voltage of the first power supply of the first sample / hold circuit and the first power supply of the second sample / hold circuit and the first value of the first current. And at least one of a voltage magnitude of the second power supply of the sample / hold circuit and the second power supply of the second sample / hold circuit is different. The method of claim 33, wherein The transistor is a p-channel transistor, And a voltage of the second power supply of the first sample / hold circuit is lower than a voltage of the second power supply of the second sample / hold circuit. The method of claim 33, wherein The transistor is an n-channel transistor, And a voltage of the second power supply of the first sample / hold circuit is higher than a voltage of the second power supply of the second sample / hold circuit. The method of claim 33, wherein The transistor is a p-channel transistor, And a voltage of the first power supply of the first sample / hold circuit is higher than a voltage of the first power supply of the second sample / hold circuit. The method of claim 33, wherein The transistor is an n-channel transistor, And a voltage of the first power supply of the first sample / hold circuit is lower than a voltage of the first power supply of the second sample / hold circuit. The method according to any one of claims 32 to 37, The first and second sample / hold circuits are respectively A first switching element electrically connected between the gate of the transistor and the input terminal; A second switching element connecting the transistor in the form of a diode at turn-on; A third switching element electrically connected between the first power supply and the transistor, A fourth switching element electrically connected between the second power supply and the transistor, and And a fifth switching element electrically connected between the transistor and the output terminal.

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