TWI376756B - Ground arch for wirebond ball grid arrays - Google Patents

Ground arch for wirebond ball grid arrays Download PDF

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Publication number
TWI376756B
TWI376756B TW093122432A TW93122432A TWI376756B TW I376756 B TWI376756 B TW I376756B TW 093122432 A TW093122432 A TW 093122432A TW 93122432 A TW93122432 A TW 93122432A TW I376756 B TWI376756 B TW I376756B
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TW
Taiwan
Prior art keywords
ground
grounding
integrated circuit
arched
circuit device
Prior art date
Application number
TW093122432A
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Chinese (zh)
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TW200507132A (en
Inventor
Chris Wyland
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Taiwan Semiconductor Mfg
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Publication of TW200507132A publication Critical patent/TW200507132A/en
Application granted granted Critical
Publication of TWI376756B publication Critical patent/TWI376756B/en

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    • H01L2924/1617—Cavity coating
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
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    • H01L2924/161—Cap
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  • Engineering & Computer Science (AREA)
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  • Wire Bonding (AREA)

Description

ί376756 九、發明說明： 【發明所屬之技術領域】 本發明係關於積體電路封裝之領域，而 多引腳半導體封裝中之焊線阻抗。 關，成】 【先前技術】 由於積體電路技術已改進至可增大在基板—既定區域内 各種裝置之密度及複雜性，對此等裝置之封裝造成一大挑 戰。例如在電腦應用中資料匯流排之寬度已從Μ，M，以 增至128位元以上。當資料在一系統中移動時，一匯= =同時交換輸出並無何不尋常之處。但該㈣交換輸:常 會造成使W之功料接地軌較因為在同時交換輸出中 所出現大的暫態電流而有之雜音。若該雜音嚴重時，接地 及：率軌會從其指定之電壓移動而造成晶片内無法預期之 打马。 在球拇陣列封裝中，常用焊線將裝置晶粒連接至封裝上 之接地。在多引腳球柵陣列中，通常是用_接地環。：等 焊線有時被f於信號料近處而藉造成—共面波導結構來 控制k號焊線之阻抗。 =國第5,872,4〇3號及M83,772號專利即是關於在一基板 上安裝-功率半導體晶粒之結構及方法。此：專利大致是 關於功率電子學，特別是關於用於一功率裝置之低阻抗大 電流導體及其製造方法。 美國第6,31 9,775 B1號專利是關於製造—積體電路封裝 之方法’特別是關於將-導電帶附裝至一積體電路晶粒及 95043.doc /〇〇〇 二專利之全部均列此做 一引線框之處理 為參考。 此一專利及前述 :傳：處理中’可用常被稱做偶入熱槽之金屬蓬狀結構 來減小熱阻。此等偶人熱槽可通地也可不通地 入熱槽至銲線之Mike土 m 男 γ 離可此過迆而無法對銲線之阻抗有顯著 ” @對銲線阻抗之控制極小。有f要對銲線阻抗提 供控制’特別是在高頻，高性能之應用上。 【發明内容】 在一實施例中有對銲線阻抗提供控制之結構。有-積體 電路裝置’包括一具有複數個接地墊、信號墊及功率墊之 積體電路及—用以安裝該積體電路之封t。該封裝包括一 具有至J/ 一個圍著該積體電路基準軌跡之接地軌跡導電路 仏在該積體電路上放置一拱形接地。此一實施例之特點 是該基準軌跡被耦合至下述者之一：一電壓基準及一接地 基準°亥貫施例之另一特點是該拱形接地包括具有介質材 料之一疊片金屬帶。 在另實施例中是討論在封裝半導體裝置晶粒時控制銲 線阻抗之方法。該方法包括界定裝置晶粒上信號及功率/ 接地墊之位置。封裝上之接地軌跡位置被加以界定。界定 接地軌跡位置後，將該裝置晶粒之信號墊及功率/接地墊 以銲線接合。在銲線及接地軌跡位置上置一包括一拱形接 地之導電路徑。該拱形接地被附裝至將拱形接地耦合至接 地軌跡位置之封裝。將該裝置晶粒及拱形接地包入—囊 内〇 95043.doc 下文中將說明其他優點及新奇特性，熟於此項技術者從 下文對此等優點及特性可有部分明白，或可從實 而知悉。 【實施方式】 本發明有心減小連接該裝置及球柵陣狀功率或接地 路徑之阻抗。此外，本發明能藉在距信號銲線預定距離處 放置一拱形接地來控制信號銲線之阻抗。 這有助於高頻應用，例如接近i咖之高頻記憶器應 用。也有助於其中信號之升高時間較通過封裝傳播延遲為 快之高速應用。藉著有較低銲線阻抗，在晶粒塾處可有較 快之升高時間，目在該墊處之升高時間是以封裝互接特性 阻抗乘以墊電容來界定。減低之封裝互接阻抗，包括銲線 在内，月b有較快升咼時間也因而有較快之積體電路裝置。 在其他應用中，拱形接地可被銲接至一穩定基準電壓而 非接地。此一應用可由特定裝置晶粒特性及電壓供應要求 來驅動。 如圖1所示’標示圖50顯示出為距拱形接地焊線距離函 數之焊線阻抗。曲線60顯示在變動距離上焊線之阻抗。各 距離上之阻抗如65所示在曲線中每一資料點上之數字。例 如，在50 μιη距離上之線阻抗約為61 〇hms。在另一例中 (未示出）’在約5 00 μηι距離上之阻抗約為119 ohms »就無 屏蔽銲線而言’其阻抗約為125 ohms。 在一實施例中，在積體電路裝置及銲線近處形成一銅條 來減小銲線阻抗。此外，經減小之銲線阻抗可減小銲線電 95043.doc 7 1376756 感及電磁干擾。使用—薄銅條能使拱形接地按照特定鲜線 及晶粒組態之要求來製作。 現參看圖2A ,按照本發明一實施例，在一晶粒及靠近銲 線之封裝間製作一低阻抗功率或通地連接。這可減小銲線 之阻杬。在一球柵陣列封裝結構1〇〇中裝入一積體電路裝 置。sh粒130被附裝至基板11〇。晶粒墊115以線12〇銲接至 封裝著地點125。 銲球105被麵合至接地軌跡14〇。此一接地軌跡“ο可為 一常用於球柵陣列t為積體電路晶粒丨3〇提供接地連接之 接地環。拱形接地170置於被銲接積體電路晶粒13〇上並透 過導電銲接150a及150b附裝至接地軌跡14〇。拱形接地17〇 有一種導電材料160及介質材料145。導電材料16〇可包括 適用於製作積體電路裝置加工及封裝該裝置之任何金屬。 。玄等材料包括但不限於銅、金、銀、鋁及彼等之合金。 圖2B為拱形接地170之斷面圖特寫。導電材料16〇及介質 材料145之厚度適於一特定封裝類型。例如，本發明可適 用於具有特別設計引線框之針柵陣列。該引線框設計成接 地引線夠寬而可允許與拱形接地有電接觸。 在-實施例甲，導電材料⑽可為—銅帶。銅帶是以傳 統方式形成亦可按照一既定晶粒大小與銲線高度及長度之 要求製作。但該帶必須有足夠厚度俾提供一自我支^二構 而經得起裝囊之嚴格要求。例如’ 25 μιη之厚度可能足 夠，在其他情形下則可用25〇㈣之厚度。該厚度全視=裝 程度及製造何物而定。導電銲接15(^與15%可為導電粘著 95043.doc 1376756 劑、銲錫或壓縮銲接’但並不一定限於這些提供電附裝之 介質材料145防止導電材料ι6〇碰到銲線12〇而造成短 路。有許多適用於拱形接地之介質材料來防止意外短路。 負類型之選擇是基於使介質常數最小而符合電位損失。 該等材料包括但不限於環氧樹脂、聚銑亞胺、聚銑胺、銲 錫屏蔽、聚四氟乙烯及特氟隆。介質當然必須耐得住銲接 加工中所遭遇之溫度。 參看圖3,也有在其中不欲將導電銲接通地之應用。按 照本發明之另一實施例，一結構2〇〇有一銲接至基板21〇之 晶粒230。晶粒230以線220從墊著地點215銲接至封裝著地 點225。具有其上置有絕緣材料245之導電部分260之拱形 接地270透過銲接25〇a，250b , 250c銲接 270之中心為彎曲而提供一附加著地點。 形銲接於其絕緣材料245上。銲接250a万 軌跡連接至銲球205，因此Μ裉诒非带技 250c銲接至基板21〇❶拱形376376756 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to the field of integrated circuit packaging, and the resistance of the bonding wire in a multi-lead semiconductor package. [Closed] [Prior Art] Since the integrated circuit technology has been improved to increase the density and complexity of various devices in a given area of a substrate, packaging of such devices poses a major challenge. For example, in computer applications, the width of the data bus has increased from Μ, M, to more than 128 bits. When data is moved in a system, it is not unusual for a sink == to exchange outputs at the same time. However, the (4) exchange transmission often results in the noise of the grounding rail of the W material compared to the large transient current appearing in the simultaneous exchange output. If the noise is severe, the ground and the rate rail will move from their specified voltage, causing unpredictable horses in the wafer. In ball thumb array packages, a common wire bond connects the device die to the ground on the package. In a multi-pin ball grid array, a _ ground ring is typically used. : Etc. The wire is sometimes caused by f near the signal material - a coplanar waveguide structure to control the impedance of the k wire. The national patents 5, 872, 4, 3 and M 83, 772 are related to the structure and method of mounting a power semiconductor die on a substrate. This: The patent is broadly about power electronics, especially with regard to low impedance large current conductors for a power device and methods of making the same. U.S. Patent No. 6,31,775 B1 is directed to a method of manufacturing an integrated circuit package, particularly with respect to attaching a conductive strip to an integrated circuit die and all of the patents of 95043.doc / 2nd patent. This is done as a reference for the processing of a lead frame. This patent and the foregoing: pass: The process can be used to reduce the thermal resistance by a metal canopy structure often referred to as an even heat sink. These coupled hot troughs can pass through the hot trough to the weld line of the Mike m m γ. However, the impedance of the weld line cannot be significantly improved. @ @The weld line impedance is extremely small. f. It is necessary to provide control on the resistance of the bonding wire 'especially in high frequency, high performance applications. [Invention] In one embodiment, there is a structure for providing control of the resistance of the bonding wire. The integrated-integrated circuit device includes one having a plurality of integrated circuits of a ground pad, a signal pad and a power pad, and a package for mounting the integrated circuit. The package includes a ground track circuit having a reference track to the J/one of the integrated circuit. An arched ground is placed on the integrated circuit. This embodiment is characterized in that the reference track is coupled to one of: a voltage reference and a ground reference. Another feature of the embodiment is the arch. The shaped ground includes a laminated metal strip having one of the dielectric materials. In another embodiment, a method of controlling the resistance of the bonding wire when packaging the die of the semiconductor device is discussed. The method includes defining the location of the signal on the device die and the location of the power/ground pad On the package The position of the grounding track is defined. After defining the position of the grounding track, the signal pad and the power/ground pad of the device die are joined by wire bonding. A conductive path including an arched ground is disposed at the position of the bonding wire and the grounding track. The arched ground is attached to the package that couples the arched ground to the grounded track position. The device die and the arched ground are enclosed in the pocket 〇95043.doc. Other advantages and novel features are described below. The advantages and characteristics of the present invention can be partially understood or understood from the following. [Embodiment] The present invention is intended to reduce the impedance of the power or ground path connecting the device and the ball grid array. The invention can control the impedance of the signal bond wire by placing an arched ground at a predetermined distance from the signal bond wire. This facilitates high frequency applications, such as proximity to high frequency memory applications of i. The high time is faster than the high speed application through the package propagation delay. By having a lower wire impedance, there can be a faster rise time at the die, and the rise time at the pad is The package interconnection characteristic impedance is multiplied by the pad capacitance. The reduced package interconnection resistance, including the bonding wire, has a faster rise time and therefore a faster integrated circuit device. In other applications, the arch The grounding can be soldered to a stable reference voltage instead of ground. This application can be driven by specific device die characteristics and voltage supply requirements. As shown in Figure 1, 'labeling 50 shows a distance from the arched ground wire. Wire bond impedance. Curve 60 shows the impedance of the wire at varying distances. The impedance at each distance is the number at each data point in the curve as indicated by 65. For example, the line impedance at a distance of 50 μη is approximately 61. 〇hms. In another example (not shown), the impedance at a distance of about 5,000 μηι is about 119 ohms » for an unshielded wire, its impedance is about 125 ohms. In one embodiment, in the product A copper strip is formed in the body circuit device and the bonding wire to reduce the bonding wire impedance. In addition, the reduced wire bond impedance reduces the inductance and electromagnetic interference of the wire. The use of a thin copper strip enables arched grounding to be made to the requirements of a particular fresh wire and die configuration. Referring now to Figure 2A, in accordance with an embodiment of the invention, a low impedance power or ground connection is made between a die and a package adjacent the wire. This reduces the resistance of the wire bond. An integrated circuit device is incorporated in a ball grid array package structure 1A. The sh particles 130 are attached to the substrate 11A. The die pad 115 is soldered to the package location 125 by wire 12. The solder ball 105 is surface-bonded to the ground trace 14〇. The grounding track “ο can be a grounding ring commonly used for the ball grid array t to provide a ground connection for the integrated circuit die 丨 3 。. The arched ground 170 is placed on the soldered integrated circuit die 13 并 and transmitted through the conductive Soldering 150a and 150b is attached to ground trace 14A. Arched ground 17 has a conductive material 160 and dielectric material 145. Conductive material 16 can include any metal suitable for use in fabricating integrated circuit devices for processing and packaging the device. Materials such as, but not limited to, copper, gold, silver, aluminum, and the like. Figure 2B is a close-up view of the arched ground 170. The thickness of the conductive material 16 and the dielectric material 145 is suitable for a particular package type. For example, the present invention is applicable to a pin grid array having a specially designed lead frame. The lead frame is designed such that the ground lead is wide enough to allow electrical contact with the arcuate ground. In the embodiment A, the conductive material (10) may be - copper. The copper strip is formed in a conventional manner and can be made according to a predetermined grain size and the height and length of the wire. However, the tape must have a sufficient thickness to provide a self-supporting structure and stand up to the strictness of the bag. Requirement. For example, the thickness of '25 μιη may be sufficient. In other cases, the thickness of 25 〇 (4) may be used. The thickness depends on the degree of loading and the manufacturing. Conductive soldering 15 (^ and 15% can be conductive adhesion) 95043.doc 1376756 Agent, solder or compression welding 'but not necessarily limited to these dielectric materials 145 providing electrical attachment to prevent the conductive material ι6 from hitting the wire 12 〇 and causing a short circuit. There are many dielectric materials suitable for arched grounding To prevent accidental short circuits. The choice of negative type is based on minimizing the dielectric constant to meet the potential loss. These materials include but are not limited to epoxy resin, poly milling imine, poly milling amine, solder shielding, polytetrafluoroethylene and Teflon. The medium must of course withstand the temperatures encountered in the soldering process. Referring to Figure 3, there is also the application in which it is not desirable to have conductive soldering to the ground. According to another embodiment of the invention, a structure 2 has a solder to The substrate 210 has a die 230. The die 230 is soldered from the padding location 215 to the package location 225 by wire 220. The arched ground 270 having the conductive portion 260 with the insulating material 245 disposed thereon is soldered 25 〇. The center of a, 250b, 250c solder 270 provides an additional location for bending. The solder is soldered to its insulating material 245. The solder is soldered to the solder ball 205, so that the solder is not soldered to the substrate 21〇. ❶ arch

介質材料可選擇有_多特性及與所用粘著劑相容者 ^ ’圖3所示之拱形形態 附裝至基板3 1 0之晶粒 參看圖4，在本發明另一實施例中， 可電銲接至封裝。一結構3〇〇有一 330。銲線320將晶粒墊著地點315耗合至封裝著地點奶 95043.doc 1376756 銲球305被耦合至地軌跡340a及340b。在此等地軌跡340a 及340b上，拱形接地370透過導電銲接35〇a及350b在拱形 接地370之介質材料245已被打開而露出拱形接地之導電材 料260之各點被耦合於其上。除導電銲接35〇a及35〇b外， 晶粒330在其申心附近有一接地區380，其上可附裝一額外 導電銲接350c。為獲得此一組態，使用人會計劃其積體電 路設計之佈局而使接地區380可構建在晶粒330中心附近。 此一接地會在設計作業早期納入特定積體電路裝置之設計 中。若設計不允許接地區在中心時，可將該接地區置於晶 粒之不同象限中。 在另一實施例中，拱形接地370形態可在35〇a及35〇b電 銲接至地軌跡340a及340b。在350c之電連接則予以省略， 因不會有中心接地380。在350c處之拱形370可粘附於晶粒 中心附近但並非電耦合。因此，拱形接地37〇在34〇a， 3 5 0a及340b，350b處提供額外之接地，及在35〇c處提供散 埶。 拱形接地經降低之電感藉著減小功率或接地由於輸入/ 輸出交換電流所引起之雜音而改善信號之完整性。用以構 建拱形接地之帶可為實心或有網1。在才共形未被耗合至地 之情形下，可藉該拱形提供一低熱阻而散放晶粒所產生之 熱來實現對封裝熱性能之改善。在接地之應用中，該拱形 藉著在晶粒上提供—遮蔽而減小電磁干擾。與封裝相組合 之該晶粒被一接地遮蔽所包圍。 圖5所示為將上述實施例應用於具有多插腳並且裝入對 95043.doc 1^/6756 應之多球/多插腳封裝中之既定裝置晶粒之流程圖。 粒 在一實施例中’可按照一系列之步驟5〇〇在—The dielectric material may be selected to have a _ multi-characteristic and compatible with the adhesive used. The dies attached to the substrate 310 are shown in the arched form shown in FIG. 3. Referring to FIG. 4, in another embodiment of the present invention, Can be electrically soldered to the package. A structure 3 has a 330. The bond wire 320 consuming the die padding location 315 to the package location milk 95043.doc 1376756 The solder balls 305 are coupled to the ground tracks 340a and 340b. On the tracks 340a and 340b, the arcuate ground 370 is coupled to the conductive material 260 through the conductive solders 35A and 350b at the points where the dielectric material 245 of the arcuate ground 370 has been opened to expose the arcuate ground. on. In addition to the conductive solders 35〇a and 35〇b, the die 330 has a land 380 near its center of the heart, to which an additional conductive solder 350c can be attached. To achieve this configuration, the user will plan the layout of their integrated circuit design so that the connection area 380 can be built near the center of the die 330. This grounding will be incorporated into the design of a particular integrated circuit device early in the design process. If the design does not allow the area to be centered, the area can be placed in different quadrants of the crystal. In another embodiment, the arcuate ground 370 configuration can be electrically welded to ground traces 340a and 340b at 35〇a and 35〇b. The electrical connection at 350c is omitted because there is no center ground 380. The arch 370 at 350c can be adhered to near the center of the die but is not electrically coupled. Thus, the arched ground 37 provides additional grounding at 34〇a, 305a and 340b, 350b, and provides divergence at 35〇c. The reduced inductance of the arched ground improves signal integrity by reducing power or ground due to noise caused by input/output switching currents. The straps used to construct the arched ground may be solid or have a mesh 1. In the case where the conformal shape is not consumed to the ground, the arch can provide a low thermal resistance to dissipate the heat generated by the crystal grains to achieve an improvement in the thermal performance of the package. In grounded applications, the arch reduces electromagnetic interference by providing a shadow on the die. The die combined with the package is surrounded by a ground shield. Figure 5 is a flow chart showing the application of the above embodiment to a given device die having multiple pins and loaded into a multi-ball/multi-pin package of the 95043.doc 1^/6756. In one embodiment, ' can be followed by a series of steps 5 -

•fj 丄· tI t BB 乂/UL =裝上實施本發明。設計者會事先界定裝置上信號及功 :接㈣之位置。最先之設計卫作是聚焦於在增大裝置 ^之同時將裝置上雜音之發生減至最小。以—適當封 j ’使用人將裝置之信號及功率/接地塾銲接至對應之 :裝著地點(步物)。完成銲接(步驟51〇)後將棋形接地 ^於銲線上㈣515)。拱形接地上之介質材料減小形成短 路之可能。以導電銲接將梹形接地附裝至封裝（步⑽〇)。 附裝拱形接地後，使用人將裝置晶教及拱形接地組合裝囊 ^步驟530)。如前文所述，换形接地可形成為在中心附近有 曰凹陷（圖3及4)而使得可用導熱枯著劑將拱形接地附裝至 晶粒中心附近。 可用許多方法在拱形與地之間造成電接觸。例如，可在 棋形之鋼與封裝接地間用一 ^ 裡等電I，诸如導電晶粒附裝 材料 Ablestik 20〇〇βΤΜ。 一在另-實施財1形可銲接至封p在此情形下，韻 種‘毁施加至封裝接地連接而使棋形接觸到鲜聚。鲜樂 被加以回流而造成連接。當 ^ 安常使用其回流溫度高於模製化合 物固化溫度之銲漿。 在另一實施例中， 之接地墊及拱形被加 縮銲接而予以連接。 表或將晶粒以線鲜至 附裝機構可為一金熱壓縮銲接而該處 以錢金然後透過熱與壓力造成一熱壓 其他方法可為用於將矽晶粒附裝至封 封裂著地點者。 95043.doc 1376756 圖6之流程圖顯示一種用於符合上述各實施例所實施製 造半導體裝置之方法。在另一實施例中，設計人期望額外 之接地及散熱而界定裝置晶粒之信號墊、功率/接地墊及 BB粒上拱形接地附裝之位置步驟6〇5。步驟6〇5通常發生於 在矽中進行任何實際設計前。但本發明可適用於任何裝置 及封裝組合。已界定裝置晶粒墊之佈置及封裝後，該裝置 之信號及功率/接地墊被銲接至對應之封裝著地點步驟 610，然後將拱形接地帶置於裝置拱形接地上並至封裝接 地步驟615。視封裝類型而定，這些可為圍繞裝置晶粒之 銲接墊或一接地環，如圖3所示之情形。此外，在一裝置/ 封裝組態中可用複數個接地帶。銲接接地帶後，可將在該 接地帶附近之裝置信號㈣線銲接至對應之封裝著地點^ 驟620。拱形接地被銲接後將封裝密封步驟。 本發明雖特別適用於球柵陣列封裝，但亦可用於具有可 附裝梹形接地區域之任何封裝。 此外，可用一個以上之拱形接地。在一實施例中，拱形 接地可構建;^ _货 > , 、 方向。將封裝/晶粒組合旋轉90度可 附裝另一拱形接地。 在另貫施例中，拱形接地可構建成具有下述組合，即 ^ ^接地附裝於裝置晶粒中心附近而將封裝/晶粒組 «，轉90度後再附裝無晶粒銲接中心之第二拱形接地。 人:用兩個以上之拱形接地來提供加強之銲線阻抗。設計 、疋達到欲有阻抗控制所需拱形接地之數目。拱形接 地之數目會Aa私I, 马日日粒大小、封裝、銲線數目等之函數。 95043.doc 12 Ϊ376756 在又一實施例中， 及裝置晶粒上形成一 蔽0 可將若干銲線織於 網。該網會被銲接 一起而在信號銲線 至地位置而提供遮 t b & 〜没逆铁至封裝接地且延伸於 銲線上來提供遮蔽但並不接觸 ^ 衣直之+拱形。在該實旆 例之變化中，該半拱形可設計成 重得觸晶粒來減小埶阻伸 並不電耦合至該封裝。 …1仁 本發明已參考若干特定實施例 上a ▲ ^丄 說明，熟於此項技術 者會知道在不脫離後文中申請專 T f寻利釭圍所定本發明之揞妯 與範圍下可有許多改冑。 【圖式簡單說明】 本發明已藉舉例及參考所附圖式 中： 飞進步砰細說明，圖式 圖1為銲線阻抗對拱形接地距離之曲線圖. 之 側面圖； 圖2A為按照本發明實施則於球柵陣列拱形接地結構 1S)倚 1 · 固马圖2A中拱形接地結構之詳細斷面圖； 圖3為按照本發明另一實施例用於球柵 地結構之側面圖； 毛、形為 圓4為按照本發明又 地結構之側面圖：……球柵陣列另，接 粗之流程圖；及 於封裝一裝置一 圖5為按照本發明一實施例封裝_裝置晶 圖6為按照本發明另一實施例所舉出用 種方式之流程圖； 95043.doc 1376756 【主要元件符號說明】 100, 200, 300 積體電路裝置 105, 205, 305 鲜球 110, 210, 310 基板 115, 215, 315 墊著地點 120, 220, 320 焊線 125, 225, 325 封裝著地點 130, 230, 330 積體電路晶粒 140, 240, 340 地軌跡 145 介質材料 245 絕緣材料 150a, 150b, 250a, 250b, 250c 導電銲接 350a, 350b, 350c 160, 260 導電材料 170, 270, 370 供形接地 380 接地區 95043.doc - 14-• fj 丄· tI t BB 乂/UL = installed to implement the present invention. The designer will pre-define the signal and work on the device: the location of (4). The first design hobby was focused on minimizing the occurrence of noise on the device while increasing the device. The appropriate signal is used to solder the signal and power/grounding of the device to the corresponding location: the location (step). After the welding is completed (step 51〇), the chess shape is grounded to the wire (4) 515). The dielectric material on the arched ground reduces the likelihood of short circuits. The 接地-shaped ground is attached to the package by conductive soldering (step (10) 〇). After attaching the arched grounding, the user assembles the device crystal and the arched grounding combination ^Step 530). As previously described, the deformed ground can be formed with a depression near the center (Figs. 3 and 4) such that the arcuate ground can be attached to the vicinity of the center of the die with a thermally conductive cleaner. Electrical contact can be made between the arch and the ground in a number of ways. For example, an electric isoelectric I can be used between the chevron-shaped steel and the package ground, such as the conductive grain attachment material Ablestik 20〇〇βΤΜ. In another case, the shape can be soldered to the seal p. In this case, the rhyme is applied to the package ground connection to make the chevron contact to the fresh gather. Fresh music is reflowed to create a connection. When it is used, the solder paste whose reflow temperature is higher than the curing temperature of the molding compound is used. In another embodiment, the ground pads and arches are joined by shrink welding. The table or the wire is fresh to the attachment mechanism, which can be a gold heat compression welding, where the gold is then heated by heat and pressure, and the other method can be used to attach the ruthenium crystal to the seal. Location. 95043.doc 1376756 The flow chart of Figure 6 shows a method for fabricating a semiconductor device in accordance with the various embodiments described above. In another embodiment, the designer desires additional grounding and heat dissipation to define the signal pad of the device die, the power/ground pad, and the position of the arcuate ground attachment on the BB grain step 6〇5. Step 6〇5 usually occurs before any actual design in the raft. However, the invention is applicable to any device and package combination. Once the device die pad is defined and packaged, the signal and power/ground pads of the device are soldered to the corresponding package location step 610, and then the arched ground strap is placed on the device arched ground and to the package grounding step 615. Depending on the type of package, these may be solder pads or a ground ring around the device die, as shown in Figure 3. In addition, multiple ground straps are available in a single device/package configuration. After soldering the ground strap, the device signal (4) wire near the ground strap can be soldered to the corresponding package location 620. The arched ground is soldered and the package is sealed. The invention is particularly well suited for use in a ball grid array package, but can be used in any package having an attachable germanet ground region. In addition, more than one arched ground can be used. In one embodiment, the arcuate ground can be constructed; ^ _ cargo > , , direction. Rotate the package/die combination by 90 degrees to attach another arched ground. In another embodiment, the arched ground can be constructed to have the following combination, that is, the grounding is attached to the vicinity of the center of the device die and the package/die group «, after 90 degrees, and then attached to the dieless soldering The second arch of the center is grounded. Person: Use more than two arched grounds to provide enhanced wire bond impedance. Design, to achieve the number of arched grounds required for impedance control. The number of arched joints will be a function of Aa private I, the size of the horse, the size of the package, the number of weld lines, and so on. 95043.doc 12 Ϊ 376756 In yet another embodiment, a mask is formed on the die of the device to sew a plurality of bond wires to the mesh. The mesh will be soldered together to provide a shield to the ground position of the signal bond to the ground b. The metal is not reversed to the package ground and extends over the bond wire to provide shielding but does not touch the ^ straight + arch. In variations of this embodiment, the semi-arched shape can be designed to re-grain the die to reduce the 埶 resistance and not electrically couple to the package. The present invention has been described with reference to a number of specific embodiments. A ▲ ^ 丄 description, those skilled in the art will know that without departing from the scope and scope of the invention as set forth in the following application. Many changes. BRIEF DESCRIPTION OF THE DRAWINGS The present invention has been described by way of example and with reference to the accompanying drawings: FIG. 1 is a graph showing the relationship between the impedance of the bonding wire and the arcing grounding distance. FIG. 2A is a The present invention is implemented in a ball grid array arched ground structure 1S). 1 is a detailed sectional view of the arched ground structure in FIG. 2A; FIG. 3 is a side view of the ball grid structure according to another embodiment of the present invention. Fig. 5 is a side view of a structure according to the present invention: a ball grid array, a thick flow chart; and a package device. Fig. 5 is a package according to an embodiment of the present invention. Crystal Figure 6 is a flow chart of a mode according to another embodiment of the present invention; 95043.doc 1376756 [Explanation of main component symbols] 100, 200, 300 Integrated circuit device 105, 205, 305 Fresh balls 110, 210 , 310 substrates 115, 215, 315 padded locations 120, 220, 320 bond wires 125, 225, 325 packaged locations 130, 230, 330 integrated circuit die 140, 240, 340 ground track 145 dielectric material 245 insulating material 150a , 150b, 250a, 250b, 250c Conductive Welding 350a, 3 50b, 350c 160, 260 Conductive material 170, 270, 370 Shaped grounding 380 Access area 95043.doc - 14-

Claims (1)

13767561376756 第93122432號申請專利範圍修正本 十、申請專利範圍： H種積體包路1置包括：~具有複數個接地墊、 4號墊及功率墊之積體電路. 0,. 电路，及一用以安裝該積體電路 ^^ ^ ^ 具有至少一個圍繞該積體電 二準執跡及一具有一拱形接地之導電路徑之封 =該梹形接地包括-介質材料與-金屬帶之堆疊，以 附加拱形接地’相對於姉形接地輯—預定量。 合至2下之積體電路二，其中該基準執跡被輕 「I芩^主^之一.一電壓基準、一 3.如請求項以積體電路裝置，其中該拱形接地有一 颁似於該積體電路裝置區域之區域。 /如請求項1之積體電路裝置，其中該拱形接地有一 預定厚度藉時供防止拱形接地與銲線結合間電接觸之 充分結構。 5. 如請求項丨之積體電路裝置，其中該棋形接地被搞 3至該積體電料置上至少—個接地位置，其中該接地 位置包括該接地軌跡及接地墊。 6. 如請求項5之積體電路裝置，其中該接地位置更包 括一在該積體電路裝置上大約中心區之位置。 、7.如請求項4之積體電路裝置，其中該拱形接地包括 k自銅金、銀、鋁及彼等合金之高度導電材料之導 體。 、8.如請求項4之積體電路裝置，其中該等高度導電材 料為包括實體帶、網及編織銲線之形式。 9.如請求項1之積體電路裝置’其中該拱形接地被轉 0503-A34019TWF2/jychen 1376756 第93122432號申請專利範圍修正本 101年4月18日修正替換頁 合至具有下述者尹至少之一之接地位置I: 錫、低共溶金屬鋒接、熱壓銲接。 ίο.如請求項3之積體電路裝置，其中該 選自了述者t至少之一 ··環氧樹腊、聚銳亞胺、= 胺、鈐錫屏蔽、聚四氟乙烯及特氟隆。 90度I1·如請求項1之積體電路農置，其中該預定量約為 12.-種^在將—半導财置日日日㈣人—封裝 f制銲線結合阻抗之方法’該方法包括：界定該裝置： 粒上之信號及功率/接地純置；界定 ^曰 跡位置；銲接該梦署<接地軌 -h μ / ㈣與功率/接地藝；提供 已括在知線及接地轨跡位置上一拱形 ，、 I中該棋形接地包括-介質材料與-金屬 供該導電路徑還包括將該封裝旋轉_預定量提^ 附加拱形接地。 叹徒供一 ^如睛求項12之方法’其中該預定量約為％声。 14.如請求項12之方法，其 又 震置設計、封裝大小]曰绩赵曰^供附加拱形接地為 15如^It 數目、及欲有阻抗之函數。 接地距焊線距離之函數。 百阻抗為一拱形 〇503-A34019TWF2/jychen 1376756 101年7月11日修正替換頁 第93122432號圖式修正頁 500Patent No. 93,312, 432, the scope of the patent application is revised. The scope of the patent application: H-type integrated package road 1 includes: ~ an integrated circuit with a plurality of grounding pads, a 4th pad and a power pad. 0,. Circuit, and one use To install the integrated circuit ^^ ^ ^ having at least one of a conductive path around the integrated body and a conductive path having an arched ground = the meandering ground includes a stack of dielectric material and metal strip, With an additional arched grounding 'relative to the 接地-shaped grounding series—predetermined amount. Integral circuit 2 of 2, wherein the reference trace is lightly "I 芩 ^ main ^ one. A voltage reference, a 3. If the request item is an integrated circuit device, wherein the arched ground has an appearance In the region of the integrated circuit device region. The integrated circuit device of claim 1, wherein the arched ground has a predetermined thickness for a sufficient structure to prevent electrical contact between the arched ground and the bonding wire. The integrated circuit device of the request item, wherein the chess ground is engaged to the integrated electrical material and at least one grounding position is provided, wherein the grounding position includes the grounding track and the grounding pad. 6. The integrated circuit device, wherein the grounding position further comprises a position of the central portion of the integrated circuit device. 7. The integrated circuit device of claim 4, wherein the arc-shaped grounding comprises k from copper gold and silver. A conductor of a highly conductive material of aluminum and their alloys. 8. The integrated circuit device of claim 4, wherein the highly conductive material is in the form of a solid strip, a mesh, and a braided wire. 1 integrated circuit device 'where The arc-shaped grounding is turned to 0503-A34019TWF2/jychen 1376756 No. 93312032 Patent application scope revision This April 18, 2011 amendment replacement page is connected to the grounding position I having at least one of the following: Tin: eutectic metal front接 、 热 热 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如Vinyl fluoride and Teflon. 90 degree I1 · The integrated circuit of claim 1 is placed, wherein the predetermined amount is about 12.----------------- Method of combining impedance with a wire' method includes: defining the device: signal on the grain and power/grounding pure; defining the position of the track; soldering the dream station<ground track-h μ / (iv) and power/grounding art; Providing an arc shape that is included in the position of the sense line and the ground track, wherein the chevature ground includes - the dielectric material and the metal for the conductive path further comprises rotating the package by a predetermined amount to provide an additional arcuate ground. The singer provides a method of seeking the item 12, wherein the predetermined amount is about % sound. 14. The method of claim 12, which in turn displaces the design and package size. The performance of the additional arched ground is 15 as a function of the number of it, and the function of the impedance. The hundred impedance is an arched 〇 503-A34019TWF2/jychen 1376756 July 11, 2011 revised replacement page No. 93112232 schema correction page 500 510 515 520 530510 515 520 530 第5圖 1376756 101年7月11日修正替換頁 第93122432號圖式修正頁Figure 5 1376756 July 11, 101 revised replacement page No. 93112232 schema correction page 600600 605 610 615 620 第6圖 625605 610 615 620 Figure 6 625
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