US11734115B2

US11734115B2 - Method and system for facilitating write latency reduction in a queue depth of one scenario

Info

Publication number: US11734115B2
Application number: US17/135,404
Authority: US
Inventors: Shu Li
Original assignee: Alibaba Group Holding Ltd
Current assignee: Alibaba Group Holding Ltd
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2023-08-22
Also published as: US20220206894A1

Abstract

One embodiment provides a system which facilitates data management. During operation, the system processes, by a storage device, a write request and data associated with the write request, wherein the storage device comprises a plurality of channels over which to access a non-volatile memory of the storage device. The system writes the data to a first data buffer of the storage device while bypassing a first interface and a memory controller. The system sends the write request to the memory controller via the first interface. The system writes, via a first channel allocated for host write operations, the data from the first data buffer to the non-volatile memory. The system performs a garbage collection operation on the data, which comprises accessing the data via a second channel allocated for garbage collection operations.

Description

BACKGROUND Field

This disclosure is generally related to the field of data storage. More specifically, this disclosure is related to a method and system for facilitating a write latency reduction in a queue depth of one scenario.

Related Art

Today, various storage systems are being used to store and access the ever-increasing amount of digital content. A storage system can include storage servers with one or more storage devices or drives (such as a solid-state drive (SSD)). Data can be stored in a non-volatile storage media of an SSD, e.g., in Not-And flash (NAND) flash. Performance-demanding applications continue to result in increasing the queue depth of a storage device to the order of the hundreds in order to achieve an enhanced throughput. In addition, parallelism continues to grow at an increasing pace in order to address or overcome the generally long write latency associated with NAND flash. While the performance of an SSD in handling a queue depth of one may not be a practical scenario, the performance in handling a queue depth of one may still be used to evaluate an SSD as a non-trivial metric of the qualifications and features of the SSD.

One current solution for increasing the performance of an SSD involves using a Peripheral Component Interconnect Express (PCIe) interface, which places the storage drive closer to the host and provide a lower latency. The Non-Volatile Memory Express (NVMe) protocol can utilize the PCIe interface in order to communicate with the host. However, a write request and associated data must travel through the PCIe interface four times (as depicted below in relation to FIG. 1 ), which can lead to challenges with reducing the latency, and also presents a challenge in obtaining a decreased write latency in the queue depth of one scenario. Thus, reducing the write latency in a queue depth of one scenario remains a challenge.

SUMMARY

In some embodiments, the system performs the garbage collection operation on the data by the following operations. The system detects a condition which triggers performing the garbage collection operation on the data. The system retrieves the data from the non-volatile memory. The system performs the garbage collection operation on the retrieved data while bypassing an error correction code (ECC)-encoding module.

In some embodiments, the system performs the garbage collection operation on the retrieved data while bypassing an ECC-encoding module by the following operations. The system performs an error correction code (ECC) decoding on the retrieved data. The system stores the decoded data in a second data buffer which stores only data related to garbage collection operations. The system performs, by a first module which protects only data related to the garbage collection operations, a data-protecting operation on the decoded data.

In some embodiments, the second data buffer and the first module comprise hardware or firmware associated with a controller of the storage device, and the first module is a redundant array of independent disks (RAID) encoding module.

In some embodiments, the first interface is a Peripheral Component Interconnect Express (PCIe) interface, and the memory controller is a Non-Volatile Memory Express (NVMe) controller.

In some embodiments, the system dynamically allocates the plurality of channels as: a first group of a first set of channels which comprise the first channel and channels allocated for only host write operations; and a second group of a second set of channels which comprise the second channel and channels allocated for only garbage collection operations. Responsive to detecting a first predetermined threshold, the system shifts the allocation of the channels between the first group and the second group.

In some embodiments, the system shifts the allocation of the channels between the first group and the second group by the following operations. The system allocates a different set of channels in the second group for only garbage collection operations, wherein the different set of channels is distinct from the second set of channels, and the system allocates a remainder of the plurality of channels in the first group for only host write operations.

In some embodiments, the write request and the data associated with the write request are processed in parallel or at a similar time by the storage device.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 presents a flowchart illustrating a method for facilitating a write operation, in accordance with the prior art.

FIG. 2A illustrates an exemplary environment for a write flow, including the command transfer and the data transfer in a linear process, in accordance with the prior art.

FIG. 2B illustrates an exemplary environment for a write flow, including a data transfer and a command transfer in a parallel process, in accordance with an embodiment of the present application.

FIG. 3 illustrates an exemplary controller, including dedicated hardware for garbage collection operations, in accordance with an embodiment of the present application.

FIG. 4 illustrates a diagram of allocated physical bands for host write operations and garbage collection operations, in accordance with an embodiment of the present application.

FIG. 5 presents a diagram illustrating horizontal band rotation for isolation of garbage collection operations, in accordance with an embodiment of the present application.

FIG. 6A presents a flowchart illustrating a method for facilitating a write latency reduction, in accordance with an embodiment of the present application.

FIG. 6B presents a flowchart illustrating a method for facilitating a write latency reduction, in accordance with an embodiment of the present application.

FIG. 6C presents a flowchart illustrating a method for facilitating a write latency reduction, in accordance with an embodiment of the present application.

FIG. 7 illustrates an exemplary computer system that facilitates data movement while bypassing system memory, in accordance with an embodiment of the present application.

FIG. 8 illustrates an exemplary apparatus that facilitates data movement by bypassing system memory, in accordance with an embodiment of the present application.

In the figures, like reference numerals refer to the same figure elements.

DETAILED DESCRIPTION

The following description is presented to enable any person skilled in the art to make and use the embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the embodiments described herein are not limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein.

Overview

The embodiments described herein provide a system which facilitates a reduction in the write latency associated with handling a queue depth of one by providing: a command transfer and a data transfer in parallel; dedicated hardware for garbage collection; and a dynamic allocation and rotation of NAND channels for each of host write operations and garbage collection operations.

As described above, performance-demanding applications continue to result in increasing the queue depth of a storage device to the order of the hundreds in order to achieve an enhanced throughput. In addition, parallelism continues to grow at an increasing pace in order to address or overcome the generally long write latency associated with NAND flash. While the performance of an SSD in handling a queue depth of one may not be a practical scenario, the performance in handling a queue depth of one may still be used to evaluate an SSD as a non-trivial metric of the qualifications and features of the SSD.

One current solution for increasing the performance of an SSD involves using a PCIe interface, which places the storage drive closer to the host and can provide a lower latency. The NVMe protocol can utilize the PCIe interface in order to communicate with the host. However, a write request and associated data must travel through the PCIe interface four times (as depicted below in relation to FIG. 1 ), which can lead to challenges in reducing the latency. These multiple data communications can also present a challenge in obtaining a decreased write latency in the queue depth of one scenario. Thus, reducing the write latency in a queue depth of one scenario remains a challenge.

The embodiments described herein address the challenge of reducing the write latency associated with a queue depth of one scenario by providing a system with several features. First, the system can transfer a write command and its associated data in parallel, which can result in saving time which may otherwise be spent on additional communications between the NVMe controller, the PCIe interface, and the host, as described below in relation to FIGS. 2A and 2B. Second, the system can isolate the impact of garbage collection operations in the queue depth of one scenario by utilizing a stand-alone buffer and a redundant array of independent disks (RAID) circuit to handle the garbage collection operations, as described below in relation to FIG. 3 . Third, the system can allocate specific bands or channels (e.g., into partitions) for host write operations and for garbage collection operations, which can eliminate the conflict between a garbage collection operation (read or write) and a host write operation, as described below in relation to FIG. 4 . The system can also rotate the partitions of bands or channels in order to balance the NAND usage and the load on each channel, as described below in relation to FIG. 5 .

Thus, the described embodiments provide a system which can reduce the write latency associated with a queue depth of one scenario, by: improving the host data movement (via a parallel transfer of a write request and associated data); removing occupation of the backend controller (via dedicated hardware for garbage collection); and eliminating conflicts between NAND channels (via dynamic rotation of allocated bands specifically for garbage collection operations and host write operations). The parallel data transfer can result in reducing the redundant wait time involved with the host interface protocol in the conventional storage system, while the isolation of the backend resources and the dynamic allocation of the NAND channels can ensure a non-interrupted and continuous programming flow to execute host write operations. These technical and technological improvements can result in addressing the challenges associated with the performance of a random write versus a sequential write pattern.

A “distributed storage system” or a “storage system” can include multiple storage servers. A “storage server” or a “storage system” can refer to a computing device which can include multiple storage devices or storage drives. A “storage device” or a “storage drive” refers to a device or a drive with a non-volatile memory which can provide persistent storage of data, e.g., a solid-state drive (SSD), or a flash-based storage device. A storage system can also be a computer system.

“Non-volatile memory” refers to storage media which may be used for persistent storage of data, e.g., flash memory of a NAND die of an SSD, magnetoresistive random access memory (MRAM), phase change memory (PCM), resistive random access memory (ReRAM), or another non-volatile memory.

A “computing device” refers to any server, device, node, entity, drive, or any other entity which can provide any computing capabilities.

The term “queue depth” refers to the number of pending input/output (I/O) requests for a volume, storage unit, or other storage device. The term “queue depth of one” refers to a scenario in which the number of pending I/O requests for the volume, storage unit, or other storage device is one.

Exemplary Write Operation in the Prior Art

FIG. 1 presents a flowchart illustrating a method 100 for facilitating a write operation, in accordance with the prior art. A storage system can include a host which communicates with an SSD. The SSD can include a controller, a Peripheral Component Interconnect Express (PCIe) interface, a Non-Volatile Memory express (NVMe) controller which can provide support for submission and completion queues, and a data buffer. The host can set the doorknob in the submission queue, which is subsequently observed by the SSD controller. The SSD controller can receive the host request and respond by retrieving the host data through the PCIe interface. Upon the host data being transferred or written to the data buffer of the SSD (and protected with a power loss protection module or unit), the SSD controller can notify the host of the completion of the data write by inserting the entry into the completion queue. The system can write the data from the data buffer to the NAND flash in an asynchronous manner. The host can access the completion queue through an interrupt mode or a polling mode in order to obtain acknowledgment for completion of the write request.

Specifically, the system inserts one entry (e.g., associated with a write request) into the submission queue (operation 102). The system sets the doorknob of the submission queue and notifies the SSD controller of the same (operation 104). The system accesses, by the controller, the submission queue to obtain the entry to be processed (operation 106). The system analyzes, by the NVMe controller, the command and processes the write request (operation 108). The system moves host data from the host memory into the SSD data buffer (operation 110). The system inserts one entry into the completion queue (operation 112). The system observes, by the host, the entry into the completion queue, and the system processes, by the host, the I/O callback (operation 114). The system notifies the SSD controller of completion of the I/O callback (operation 116), and the operation returns.

Write Operation in the Prior Art vs. Embodiment with Parallel Command/Data Transfer

FIG. 2A illustrates an exemplary environment 200 for a write flow, including a command transfer and a data transfer in a linear process, in accordance with the prior art. Environment 200 can include a host 210 which communicates with an SSD 220, which can include: a PCIe interface 222; an NVMe controller 224; a flash controller 226; a write buffer 228; a NAND interface 230; and

NAND flash memory

232, 234, and 236. During operation, in processing a write request, the submission queue entry and the NVMe command analysis (e.g.,

communications

240 and 242, corresponding to operations 102-108 of a write operation in a conventional system) occur prior to the actual data transfer from the host to the write buffer (e.g., as indicated by the dashed

arrows

244, 246, and 248). The data can subsequently be written from write buffer 228 to NAND flash 232-236 via flash controller 226 and NAND interface 230. Thus, the data transfer from host 210 to write buffer 228 cannot occur until the write request has first been processed by PCIe interface 272 and NVMe controller 274 (via communications 240 and 242), which can result in an increased latency in executing the write operation.

FIG. 2B illustrates an exemplary environment 250 for a write flow, including the data transfer and the command transfer in a parallel process, in accordance with an embodiment of the present application. Similar to environment 200, environment 250 can include a host 260 which communicates with an SSD 270, which can include: a PCIe interface 272; an NVMe controller 274; a flash controller 276; a write buffer 278; a NAND interface 280; and

NAND flash memory

282, 284, and 286. Write buffer 278 can include a host memory 279, which can be used to store data which is transferred from or received directly from host 260 while bypassing PCIe interface 272 and NVMe controller 274. Host memory 279 can be a region or portion of write buffer 278, which region is physically allocated from write buffer 278 and can be logically associated with host 260. That is, host memory 279 can logically belong to or operate under the control of host 260, but the data can physically accomplish traveling from host 260 to SSD 270 through PCIe 272.

During operation, in processing a write request, the submission queue entry and the NVMe command analysis (e.g.,

communications

240 and 242, corresponding to operations 102-108 of a write operation in a conventional system) can occur in parallel with the actual data transfer from host 260 to host memory 279 of write buffer 278 (e.g., as indicated by dashed arrows 294 and 296). That is, host 260 can send a write request and associated data, where the write request is processed via

communications

290 and 292 by PCIe interface 272 and NVMe controller 274, and the data can be processed by a direct transfer to host memory 279 via

communications

294 and 296. By the time of completion of analysis of the write request by NVMe controller 274 (via communications 290 and 292), the associated data may already be stored in host memory 279 of write buffer 279 of SSD 270. Because the data is already stored in write buffer 278, the system can write the data from write buffer 278 to NAND flash 282-286 without waiting for

communications

290 and 292 to finish, and without waiting for SSD 270 to retrieve the associated data from host 260 (as depicted above in relation to FIG. 2A).

Thus, the data transfer from the host to the write buffer can occur in parallel and separate from the write request being processed by the PCIe interface and the NVMe controller, which in turn can result in the data being written to the NAND flash without waiting for completion of the write request processing (e.g., communications 290 and 292). This parallel processing of the write command and the associated data can result in a reduced latency in executing the write operation, which in turn can result in a reduced latency for the queue depth of one scenario.

Exemplary SSD Controller with Dedicated Hardware for Garbage Collection Operations

As depicted above in relation to environment 250 of FIG. 2B, performing a sequential write operation can be straightforward, as the asynchronous write from the data buffer (e.g., write buffer 278) to the NAND flash (e.g., 282-286) can depend mainly on the throughput of the backend operations. However, in performing a random write operation, the system may trigger a garbage collection operation, which can, from time to time, consume the resources of the SSD controller and the NAND channels. This can result in an unstable performance for the SSD, e.g., based on the introduction of the uncontrollable (or uncontrolled) garbage collection operations. Furthermore, read operations generally take higher priority than write operations. Thus, on a given channel, a garbage collection read operation would take priority over a host write operation, which can result in delaying the host write operation and may also result in congestion or delay in executing the host write operation.

The embodiments described herein address the instability associated with these uncontrollable garbage collection operations by providing dedicated hardware (or firmware) to isolate the impact of the garbage collection operations in the queue depth of one scenario. In general, during a garbage collection operation, the system reads valid data from a block or other unit to be recycled from NAND flash, and writes the valid data back into a new block or other unit of the NAND flash. In a conventional operation, the data buffer and the RAID module are shared by both garbage collection operations and host write operations.

The described embodiments instead provide a stand-alone data buffer and a RAID circuit to handle solely and specifically the garbage collection operations. The stand-alone data buffer and RAID circuit can be implemented to handle only operations and data related to garbage collection operations. The system can read raw data from the NAND, an ECC decoder can remove the errors from the raw data to obtain a decoded codeword, and a cyclic redundancy check (CRC) module can check the sanity or integrity of the data. Because the decoded codeword includes the ECC parity, the recycled data can bypass the ECC encoder and use its specific RAID circuit to accumulate the RAID parity, which can also be written into the NAND flash, as described below in relation to FIG. 3 .

FIG. 3 illustrates an exemplary controller 310, including dedicated hardware for garbage collection operations, in accordance with an embodiment of the present application. Controller 310, in an environment 300, can include: a host interface 312; a CRC module 314; an ECC encoder 316; a garbage collection (GC) RAID module 318; a garbage collection (GC) buffer 320; an ECC decoder 322; and a NAND interface 280, which communicates with

NAND flash memory

282, 284, and 286, via, respectively, a channel_1 330, a channel_2 332, and a channel_N 334.

During operation, the system can detect a condition which triggers performing a garbage collection process on certain data (e.g., valid data associated with a block to be recycled). The system can retrieve the certain data from, e.g., NAND flash 284 via channel_2 332, via NAND interface 280. The data can be transmitted to ECC decoder 322, which can perform an ECC decoding on the certain data to obtain a decoded codeword. ECC decoder 322 can send the decoded codeword to CRC module 314, which can perform a CRC to ensure the sanity or integrity of the data. The decoded (and CRC checked) data can then be stored in a specific GC buffer 320. GC buffer 320 can be a data buffer which stores only data related to garbage collection operations. The stored GC data can be sent to GC RAID module 318, which can protect only data related to garbage collection operations. The data can be subsequently written to an appropriate block (e.g., an available or open block) of

NAND flash

282, 284, or 286, via, respectively, one of

channels

330, 332, 334, thus bypassing ECC encoder 316.

GC RAID module

318 and GC buffer 320 can be implemented as dedicated hardware or firmware of SSD controller 310. Thus, by implementing a specific data buffer and data-protecting module for the garbage collection operations, the described embodiments can eliminate the shared usage of backend components (by both background garbage collection operations and host write operations) while processing data to be written to the non-volatile memory. This can result in solving the bottleneck in the performance (latency) of a host write operation which is conventionally caused by a read engine (which, in a conventional system, would need to handle both host flow operations and garbage collection operations). In turn, this can result in reducing the write latency associated with host write operations, including the queue depth of one scenario.

Allocated Bands/Channels for Host Write Operations and Garbage Collection Operations; and Exemplary Band Rotation

Additionally, the described embodiments can dynamically allocate bands, which can include a set of channels, to each of host write operations and garbage collection operations. That is, when writing data from the controller to the NAND flash, the system can allocate specific bands of channels, such that host write operations can be processed on a first set of channels, while garbage collection operations can be processed on a different second set of channels, as described below in relation to FIG. 4 . The system can also rotate the allocated bands or groups or set of channels, to balance both the usage of the NAND flash and the load on each channel, as described below in relation to FIG. 5 .

FIG. 4 illustrates a diagram 400 of allocated physical bands for host write operations and garbage collection operations, in accordance with an embodiment of the present application. Diagram 400 can include: an SSD controller 402; NAND blocks 410 and 426, including at least, respectively, blocks 412 and 428, and accessed via a channel_1 (CH_1) 442; NAND blocks 414 and 430, including at least, respectively, blocks 416 and 432, and accessed via a channel_k (CH_k) 444; NAND blocks 418 and 434, including at least, respectively, blocks 420 and 436, and accessed via a channel_k+1 (CH_k+1) 446; and

NAND blocks

422 and 438, including at least, respectively, blocks 424 and 440, and accessed via a channel_n (CH_n) 448.

The system can allocate for host write operations a host write band 460, such as a first group of a first set of channels for host write operations. The system can also allocate for garbage collection operations a garbage collection band 470, such as a second group of a second set of channels for garbage collection operations. Host write band 460 can include

channels

442 and 444, while garbage collection band 470 can include

channels

446 and 448.

During operation, a host read operation can occur on any channel at any time, e.g., at indicated by a host read 464 occurring via channel_k 444 of host write band 460 and a host read operation 476 occurring via channel_n 448 of garbage collection band 470. The system can process a host write operation 462 by accessing a block of NAND flash memory via an allocated channel of host write band 460, e.g., via channel_1 442. The system can also process a garbage collection read 472 or a garbage collection write 474 by accessing a block of NAND flash memory via an allocated channel of garbage collection band 470, e.g., via channel_k+1 446.

Thus, garbage collection operations (such as 472 and 474) can occur on (a channel of) a specifically GC-allocated band, which does not occupy or share space or resources of the page buffer and NAND channels used to execute host write operations. In general, the queue depth of one scenario does not generate a throughput high enough to saturate multiple NAND channels in the backend, thus the host write band is sufficient to ensure the Quality of Service (QoS) for the performance of a random write operation.

Furthermore, based a first predetermined threshold, the system can dynamically rotate the partition all of the NAND channels to transverse the NAND pages in a RAID group. The first predetermined threshold can be based on, e.g., a periodic interval; another predetermined time interval; historical usage of a channel or channels; a current load across the channels; an expected, predicted, or estimated load; a current traffic analysis; and an algorithm which ensures wear-leveling. This allows the system to balance out the both the usage of the NAND flash and the load on each channel.

FIG. 5 presents a diagram 500 illustrating horizontal band rotation for isolation of garbage collection operations, in accordance with an embodiment of the present application. Diagram 500 illustrates a dynamic allocation or shifting of channels in a host write band and a garbage collection band at a plurality of times t0, t1, t2, and t3.

At a time t0, a host write band 510 can include channels (e.g., 1-6) allocated for host write operations, while a garbage collection band 512 can include channels (e.g., 7-8) allocated for garbage collection operations. At a subsequent time t1, a garbage collection band 520 can include channels (e.g., 1-2) allocated for garbage collection operations, while a host write band 522 can include channels (e.g., 3-8) allocated for host write operations. At a time t2, a host write band 530 and a host write band 534 can include channels (e.g., respectively, 1-2 and 5-8) allocated for host write operations, while a garbage collection band 532 can include channels (e.g., 3-4) allocated for garbage collection operations. At a time t3, a host write band 540 and a host write band 544 can include channels (e.g., respectively, 1-4 and 7-8) allocated for host write operations, while a garbage collection band 542 can include channels (e.g., 5-6) allocated for garbage collection operations.

Thus, diagram 500 depicts how the system can partition the NAND channels into bands, and can further adjust the partition of the NAND channels into the bands over time. The system can rotate or shift the allocation of the channels into each band, which allows the GC band to rotate through all other pages covered in the same RAID group. This dynamic partition, allocation, and rotation can ensure that all pages in a RAID group are covered, while also ensuring a decrease in the write latency associated with host write operations, including a queue depth of one scenario.

Exemplary Method for Facilitating a Write Latency Reduction

FIG. 6A presents a flowchart 600 illustrating a method for facilitating a write latency reduction, in accordance with an embodiment of the present application. During operation, the system processes, by a storage device, a write request and data associated with the write request, wherein the storage device comprises a plurality of channels over which to access a non-volatile memory of the storage device (operation 602). The system writes the data to a first data buffer of the storage device while bypassing a first interface and a memory controller (operation 604). The system sends the write request to the memory controller via the first interface (operation 606). The system writes, via a first channel allocated for host write operations, the data from the first data buffer to the non-volatile memory (operation 608). The system performs a garbage collection operation on the data, which comprises accessing the data via a second channel allocated for garbage collection operations (operation 610). The operation continues at Label A of FIG. 6B.

FIG. 6B presents a flowchart 620 illustrating a method for facilitating a write latency reduction, in accordance with an embodiment of the present application. The system can perform a garbage collection operation on retrieved data while bypassing an ECC-encoding module. The system performs an error correction code (ECC) decoding on the retrieved data (operation 622). The system stores the decoded data in a second data buffer which stores only data related to garbage collection operations (operation 624). The system performs, by a first module which protects only data related to the garbage collection operations, a data-protecting operation on the decoded data (operation 626). The second data buffer and the first module can comprise hardware or firmware associated with a controller of the storage device, and the first module can be a redundant array of independent disks (RAID) encoding module, as described above in relation to FIG. 3 .

FIG. 6C presents a flowchart 640 illustrating a method for facilitating a write latency reduction, in accordance with an embodiment of the present application. The operations of flowchart 640 can occur prior to or concurrent with the operations of

flowcharts

600 and 620. The system dynamically allocates the plurality of channels as: a first group of a first set of channels which comprise the first channel and channels allocated for only host write operations; and a second group of a second set of channels which comprise the second channel and channels allocated for only garbage collection operations (operation 642). If the system does not detect a first predetermined threshold (decision 644), the operation returns to decision 644 until the first predetermined threshold is detected.

If the system does not detect a first predetermined threshold (decision 644), the system shifts the allocation of the channels between the first group and the second group (operation 646). The system allocates a different set of channels in the second group for only garbage collection operations, wherein the different set of channels is distinct from the second set of channels (operation 648), and the system allocates a remainder of the plurality of channels in the first group for only host write operations (operation 650).

Exemplary Computer System and Apparatus

FIG. 7 illustrates an exemplary computer system 700 that facilitates data movement while bypassing system memory, in accordance with an embodiment of the present application. Computer system 700 includes a processor 702, a volatile memory 706, and a storage device 708. In some embodiments, computer system 700 can include a controller 704 (indicated by the dashed lines). Volatile memory 706 can include, e.g., random access memory (RAM), that serves as a managed memory, and can be used to store one or more memory pools. Storage device 708 can include persistent storage which can be managed or accessed via processor 702 (or controller 704). Furthermore, computer system 700 can be coupled to peripheral input/output (I/O) user devices 710, e.g., a display device 711, a keyboard 712, and a pointing device 714. Storage device 708 can store an operating system 716, a content-processing system 718, and data 734.

Content-processing system 718 can include instructions, which when executed by computer system 700, can cause computer system 700 or processor 702 to perform methods and/or processes described in this disclosure. Specifically, content-processing system 718 can include instructions for receiving and transmitting data packets, including data to be read or written, and an input/output (I/O) request (e.g., a read request or a write request) (communication module 720).

Content-processing system 718 can further include instructions for processing, by a storage device, a write request and data associated with the write request, wherein the storage device comprises a plurality of channels over which to access a non-volatile memory of the storage device (request-processing module 722). Content-processing system 718 can include instructions for writing the data to a first data buffer of the storage device while bypassing a first interface and a memory controller (data-writing module 724). Content-processing system 718 can include instructions for sending the write request to the memory controller via the first interface (request-processing module 722). Content-processing system 718 can include instructions for writing, via a first channel allocated for host write operations, the data from the first data buffer to the non-volatile memory (data-writing module 724). Content-processing system 718 can include instructions for performing a garbage collection operation on the data, which comprises accessing the data via a second channel allocated for garbage collection operations (garbage collection-managing module 728).

Content-processing system 718 can additionally include instructions for detecting a condition which triggers performing the garbage collection operation on the data (threshold-detecting module 732). Content-processing system 718 can include instructions for retrieving the data from the non-volatile memory (communication module 720). Content-processing system 718 can include instructions for performing the garbage collection operation on the retrieved data while bypassing an error correction code (ECC)-encoding module (garbage collection-managing module 728 and ECC-bypassing module 730).

Data

734 can include any data that is required as input or generated as output by the methods and/or processes described in this disclosure. Specifically, data 734 can store at least: data; a request; a read request; a write request; an input/output (I/O) request; data or metadata associated with a read request, a write request, or an I/O request; formatted data; encoded data; CRC data; CRC-checked data; ECC-encoded or ECC-decoded data; an indicator or identifier of a storage drive, an interface, a memory controller, a write buffer, a host memory in the write buffer, a channel, and a NAND flash block or unit; a condition which triggers a garbage collection process; a predetermined threshold for shifting an allocation of channels to bands; data marked to be recycled or on which a garbage collection process is to be performed; an indicator of a GC-specific data buffer or a GC-specific RAID or data-protecting module; raw data; ECC-encoded data; a codeword; a decoded codeword; an indicator of a channel, a band, an allocated channel to a band; an indicator or identifier of a host write band or a garbage collection band; a channel allocated for host write operations; a channel allocated for garbage collection operations; a first set of channels; a second set of channels; and a different set of channels.

FIG. 8 illustrates an exemplary apparatus 800 that facilitates data movement by bypassing system memory, in accordance with an embodiment of the present application. Apparatus 800 can comprise a plurality of units or apparatuses which may communicate with one another via a wired, wireless, quantum light, or electrical communication channel. Apparatus 800 may be realized using one or more integrated circuits, and may include fewer or more units or apparatuses than those shown in FIG. 8 . Furthermore, apparatus 800 may be integrated in a computer system, or realized as a separate device or devices capable of communicating with other computer systems and/or devices.

Apparatus 800 can comprise modules or units 802-814 which are configured to perform functions or operations similar to modules 720-732 of computer system 700 of FIG. 7 , including: a communication unit 802; a request-processing unit 804; a data-writing unit 806; a channel-allocating unit 808; a garbage collection-managing unit 810; an ECC-bypassing unit 812; and a threshold-detecting unit 814.

The data structures and code described in this detailed description are typically stored on a computer-readable storage medium, which may be any device or medium that can store code and/or data for use by a computer system. The computer-readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media capable of storing computer-readable media now known or later developed.

The methods and processes described in the detailed description section can be embodied as code and/or data, which can be stored in a computer-readable storage medium as described above. When a computer system reads and executes the code and/or data stored on the computer-readable storage medium, the computer system performs the methods and processes embodied as data structures and code and stored within the computer-readable storage medium.

Furthermore, the methods and processes described above can be included in hardware modules. For example, the hardware modules can include, but are not limited to, application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), and other programmable-logic devices now known or later developed. When the hardware modules are activated, the hardware modules perform the methods and processes included within the hardware modules.

The foregoing embodiments described herein have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the embodiments described herein to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the embodiments described herein. The scope of the embodiments described herein is defined by the appended claims.

Claims

What is claimed is:

1. A computer-implemented method, comprising:

processing, by a storage device, a write request and data associated with the write request, wherein the storage device comprises a plurality of channels over which to access a non-volatile memory of the storage device;

writing the data to a first data buffer of the storage device while bypassing a first interface and a memory controller;

sending the write request to the memory controller via the first interface;

writing, via a first channel allocated for host write operations, the data from the first data buffer to the non-volatile memory; and

performing a garbage collection operation on the data, which comprises:

detecting a condition which triggers performing the garbage collection operation on the data;

accessing the data via a second channel allocated for garbage collection operations;

retrieving the data from the non-volatile memory; and

performing the garbage collection operation on the retrieved data while bypassing an error correction code (ECC)-encoding module.

2. The method of claim 1, wherein performing the garbage collection operation on the retrieved data while bypassing an ECC-encoding module comprises:

performing an error correction code (ECC) decoding on the retrieved data;

storing the decoded data in a second data buffer which stores only data related to garbage collection operations; and

performing, by a first module which protects only data related to the garbage collection operations, a data-protecting operation on the decoded data.

3. The method of claim 2,

wherein the second data buffer and the first module comprise hardware or firmware associated with a controller of the storage device, and

wherein the first module is a redundant array of independent disks (RAID) encoding module.

4. The method of claim 1,

wherein the first interface is a Peripheral Component Interconnect Express (PCIe) interface, and

wherein the memory controller is a Non-Volatile Memory Express (NVMe) controller.

5. The method of claim 1, further comprising:

dynamically allocating the plurality of channels as:

a first group of a first set of channels which comprise the first channel and channels allocated for only host write operations; and

a second group of a second set of channels which comprise the second channel and channels allocated for only garbage collection operations; and

responsive to detecting a first predetermined threshold, shifting the allocation of the channels between the first group and the second group.

6. The method of claim 5, wherein shifting the allocation of the channels between the first group and the second group comprises:

allocating a different set of channels in the second group for only garbage collection operations, wherein the different set of channels is distinct from the second set of channels; and

allocating a remainder of the plurality of channels in the first group for only host write operations.

7. The method of claim 1, wherein the write request and the data associated with the write request are processed in parallel or at a similar time by the storage device.

8. A computer system, comprising:

a processor; and

a memory coupled to the processor and storing instructions which, when executed by the processor, cause the processor to perform a method, the method comprising:

sending the write request to the memory controller via the first interface;

performing a garbage collection operation on the data, which comprises:

retrieving the data from the non-volatile memory; and

9. The computer system of claim 8, wherein performing the garbage collection operation on the retrieved data while bypassing an ECC-encoding module comprises:

performing an error correction code (ECC) decoding on the retrieved data;

10. The computer system of claim 9,

11. The computer system of claim 8,

12. The computer system of claim 8, wherein the method further comprises:

dynamically allocating the plurality of channels as:

13. The computer system of claim 12, wherein shifting the allocation of the channels between the first group and the second group comprises:

14. The computer system of claim 9, wherein the write request and the data associated with the write request are processed in parallel or at a similar time by the storage device.

15. A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method, the method comprising:

sending the write request to the memory controller via the first interface;

performing a garbage collection operation on the data, which comprises:

retrieving the data from the non-volatile memory; and

16. The storage medium of claim 15, wherein performing the garbage collection operation on the retrieved data while bypassing an ECC-encoding module comprises:

performing an error correction code (ECC) decoding on the retrieved data;

17. The storage medium of claim 15, wherein the method further comprises:

dynamically allocating the plurality of channels as:

responsive to detecting a first predetermined threshold, shifting the allocation of the channels between the first group and the second group, which comprises: