US20070139089A1 - Delay locked loop with precision contolled delay - Google Patents

Delay locked loop with precision contolled delay Download PDF

Info

Publication number
US20070139089A1
US20070139089A1 US10/581,786 US58178603A US2007139089A1 US 20070139089 A1 US20070139089 A1 US 20070139089A1 US 58178603 A US58178603 A US 58178603A US 2007139089 A1 US2007139089 A1 US 2007139089A1
Authority
US
United States
Prior art keywords
delay
signal
branch
component
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US10/581,786
Other versions
US7456664B2 (en
Inventor
Harald Jacobsson
Spartak Gevorgian
Thomas Lewin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cluster LLC
HPS Investment Partners LLC
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Assigned to TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) reassignment TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GEVORGIAN, SPARTAK, JACOBSSON, HARALD, LEWIN, THOMAS
Publication of US20070139089A1 publication Critical patent/US20070139089A1/en
Application granted granted Critical
Publication of US7456664B2 publication Critical patent/US7456664B2/en
Assigned to HIGHBRIDGE PRINCIPAL STRATEGIES, LLC (AS COLLATERAL AGENT) reassignment HIGHBRIDGE PRINCIPAL STRATEGIES, LLC (AS COLLATERAL AGENT) LIEN (SEE DOCUMENT FOR DETAILS). Assignors: OPTIS CELLULAR TECHNOLOGY, LLC
Assigned to WILMINGTON TRUST, NATIONAL ASSOCIATION (AS COLLATERAL AGENT) reassignment WILMINGTON TRUST, NATIONAL ASSOCIATION (AS COLLATERAL AGENT) SECURITY AGREEMENT Assignors: OPTIS CELLULAR TECHNOLOGY, LLC
Assigned to CLUSTER LLC reassignment CLUSTER LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
Assigned to OPTIS CELLULAR TECHNOLOGY, LLC reassignment OPTIS CELLULAR TECHNOLOGY, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CLUSTER LLC
Assigned to HIGHBRIDGE PRINCIPAL STRATEGIES, LLC, AS COLLATERAL AGENT reassignment HIGHBRIDGE PRINCIPAL STRATEGIES, LLC, AS COLLATERAL AGENT ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OPTIS CELLULAR TECHNOLOGY, LLC
Assigned to HIGHBRIDGE PRINCIPAL STRATEGIES, LLC, AS COLLATERAL AGENT reassignment HIGHBRIDGE PRINCIPAL STRATEGIES, LLC, AS COLLATERAL AGENT CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE TO READ "SECURITY INTEREST" PREVIOUSLY RECORDED ON REEL 032786 FRAME 0546. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Assignors: OPTIS CELLULAR TECHNOLOGY, LLC
Assigned to OPTIS CELLULAR TECHNOLOGY, LLC reassignment OPTIS CELLULAR TECHNOLOGY, LLC RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: HPS INVESTMENT PARTNERS, LLC
Adjusted expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter

Definitions

  • the present invention relates to a Delay-Locked Loop (DLL) circuit, comprising input means for a signal that is to be delayed, said input means comprising means for splitting said input signal into a first and a second branch, where the signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a reference for the delay caused by the delay component in the first branch
  • DLL Delay-Locked Loop
  • Time delay circuits are important building blocks in many electronic systems, such as oscillators, measurement instruments, frequency multipliers, wave-form generators and data and clock recovery circuitry. Most commonly, the desired delay is achieved by use of transmission lines, active circuits, cables (optical or electrical), surface acoustic wave (SAW) circuitry, or magnetostatic wave (MSW) circuitry.
  • SAW surface acoustic wave
  • MSW magnetostatic wave
  • the delay can be varied by a control signal.
  • a control signal there is a desire for the delay to be a certain fraction of a period, or an integer multiple of such a fraction.
  • a Delay-Locked-Loop is often used.
  • a DLL is designed by means of active circuits, most commonly inverters.
  • N a fixed number, of delay cells is used, which means that only phase delays of M/N*360°, where 0 ⁇ M ⁇ N, can be obtained.
  • the delay can be chosen by means of a control signal, and where the delay can be chosen in a continuous range, preferably in the entire range of 0-360 degrees.
  • a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting said input signal into a first and a second branch.
  • the signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch.
  • the delay component is a passive tunable delay line, with the circuit comprising tuning means for the tunable delay line.
  • the tuning means are affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay.
  • the delay component of the circuit is continuously tunable, and preferably passive, such as a tunable ferroelectric delay line.
  • a tunable ferroelectric delay line As alternatives to the tunable ferroelectric delay line, mention can be made of SAW-circuits or MSW-circuits.
  • FIG. 1 shows a schematic block diagram of a known delay-locked loop
  • FIG. 2 schematically shows the principle behind a delay-locked loop according to the invention
  • FIG. 3 shows a more detailed drawing of a delay component of the invention.
  • the circuit 100 in FIG. 1 comprises first input means 110 for an input signal, V in , which input means split the input signal into a first and a second input branch.
  • V in delay-locked loop
  • the signal in the first input branch of the DLL-circuit is input to a tunable delay component 120 , which component thus also has an input possibility for the input of a control or tuning signal, said control signal controlling the delay to which the input signal V in is exposed.
  • the output from the delay component 120 is split into a first and a second output branch, where the first output branch is used as an output signal from the DLL-circuit, the signal having the desired delay.
  • the signal in the second output branch from the delay component 120 is used as one of two input signals to a phase detector 150 .
  • the signal in the second input branch of the DLL is used as the other of the two input signals to the phase detector 150 .
  • the phase detector serves to detect the phase difference or delay between the non-delayed signal and the output signal from the delay component.
  • the output signal from the phase detector corresponds to the phase difference, and is used as the control signal for the delay component 120 in the first input branch of the DLL-circuit.
  • the output signal from the phase detector is passed through a low-pass filter 140 before being input to the delay component 120 .
  • the DLL of FIG. 1 can thus provide a phase delay of an input signal, with the phase delay being varied by means of a control signal.
  • the most commonly used building block in the delay component are active circuits, usually inverters.
  • inverters the use of, for example, inverters in the DLL will limit the available delays to a certain number of discrete steps.
  • FIG. 2 a DLL 200 according to the invention is shown, which overcomes this problem of known DLL:s.
  • the DLL 200 of the invention in similarity to earlier known DLL:s, comprises an input means 210 for a signal V in which is to be delayed.
  • the input means 210 split the input signal into a first and a second branch, and the signal in the first branch is connected to a component 220 for delaying the signal.
  • the DLL 200 of the invention makes use of a passive tunable delay line 220 as the delaying component.
  • the detailed function and design of this building block 220 of the DLL 200 will be elaborated upon in more detail below, in connection with FIG. 3 .
  • the tunable delay line 220 is that it is possible to tune the delay line so that the electrical distance to be covered by a signal in the line always remains the same, regardless of the frequency of the signal. This means that the phase of a signal entering the delay line 220 will always be the same at a fixed point in the delay line, regardless of the frequency or wavelength of the signal.
  • phase at each of these points is known, either by measurement or calculation, and is, by way of example, shown as 90°, 180°, 270° and 360°. As mentioned earlier, the phase at these points will always remain essentially the same, regardless of the wavelength of the input signal, if the delay line is kept properly tuned, which will be explained below.
  • the input signal in the second branch is used as a non-delayed reference for the delay caused by the tuning line in the first branch, which is achieved by means of the input signal in the second branch being connected to a means 250 for phase comparison, in the example shown a phase detector 250 .
  • the phase detector 250 is connected to a point in the delay line with a well defined phase shift, in the example shown 360°.
  • the two input signals to the phase detector are the non-delayed signal from the first branch, and the signal from the second branch which has been shifted 360°.
  • the phase difference between these two signals should accordingly be zero, resulting in an output signal from the phase detector which corresponds to zero phase difference.
  • the output signal from the phase detector 250 is used as a reference signal or control signal for controlling the tunable delay line 220 , preferably after having been passed through a low pass filter 240 .
  • the filtered output signal from the phase detector 250 is then used as input to a control means 230 for controlling the electrical distance which a signal passing through the delay line will have to cover. In this way, the electrical distance can be kept at a constant and desired value, regardless of the wavelength of the input signal V in .
  • phase delays shown in FIG. 2 and mentioned above are only examples, any phase difference can be obtained from the DLL 200 by accessing the proper points in the delay line.
  • phase detector 250 could in an alternative embodiment compare with another phase position than 360 degrees.
  • a tunable delay line 220 as used in FIG. 2 is shown in more detail: as mentioned previously, the delay line 220 is preferably a tunable ferroelectric delay line.
  • a delay line can consist of the components shown in FIG. 3 : an electrical conductor 305 is supported by a dielectric material 310 which is a ferroelectric material. The ferroelectric material in turn rests on a ground plane 315 .
  • the control signal to the control means 230 shown in FIG. 2 is connected so that it applies a voltage, V TUNE between the conductor 305 and the ground plane 315 , thereby altering the dielectric constant ⁇ of the material 310 , which causes the electrical distance to be covered by a wave through the component 220 to vary as desired.
  • control signal V TUNE
  • an electrical component such as a resistor or an inductance. This is in order to provide high impedance for the signal, but to simultaneously let through a DC or low frequency bias voltage.

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Networks Using Active Elements (AREA)
  • Gyroscopes (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Dram (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

The invention discloses a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting the input signal into a first and a second branch. The signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch. The delay component is a passive tunable delay line, and the circuit comprises tuning means for the tunable delay line, the tuning means being affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay. Suitably, the delay component is continuously tunable, for example a tunable ferroelectric delay line.

Description

    TECHNICAL FIELD OF THE INVENTION
  • The present invention relates to a Delay-Locked Loop (DLL) circuit, comprising input means for a signal that is to be delayed, said input means comprising means for splitting said input signal into a first and a second branch, where the signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a reference for the delay caused by the delay component in the first branch
    • STATE OF THE ART
  • Time delay circuits are important building blocks in many electronic systems, such as oscillators, measurement instruments, frequency multipliers, wave-form generators and data and clock recovery circuitry. Most commonly, the desired delay is achieved by use of transmission lines, active circuits, cables (optical or electrical), surface acoustic wave (SAW) circuitry, or magnetostatic wave (MSW) circuitry.
  • It is often desired, and indeed sometimes required, that the delay can be varied by a control signal. Commonly, there is a desire for the delay to be a certain fraction of a period, or an integer multiple of such a fraction. In such cases, a Delay-Locked-Loop (DLL) is often used. Usually, a DLL is designed by means of active circuits, most commonly inverters. However, in such DLL:s, a fixed number, N, of delay cells is used, which means that only phase delays of M/N*360°, where 0<M<N, can be obtained.
    • SUMMARY OF THE INVENTION
  • Accordingly, as described above, there is a need for a DLL-type circuit where the delay can be chosen by means of a control signal, and where the delay can be chosen in a continuous range, preferably in the entire range of 0-360 degrees.
  • This need is addressed by the present invention in that it discloses a delay-locked loop circuit with input means for a signal that is to be delayed, the input means comprising means for splitting said input signal into a first and a second branch.
  • The signal in the first branch is connected to a component for delaying the signal, and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch. According to the invention, the delay component is a passive tunable delay line, with the circuit comprising tuning means for the tunable delay line.
  • The tuning means are affected by said reference signal, and the first branch comprises output means for outputting a delayed signal with a chosen phase delay.
  • Suitably, the delay component of the circuit is continuously tunable, and preferably passive, such as a tunable ferroelectric delay line. As alternatives to the tunable ferroelectric delay line, mention can be made of SAW-circuits or MSW-circuits.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The invention will be described in more detail in the following, with reference to the appended drawings, where
  • FIG. 1 shows a schematic block diagram of a known delay-locked loop, and
  • FIG. 2 schematically shows the principle behind a delay-locked loop according to the invention, and
  • FIG. 3 shows a more detailed drawing of a delay component of the invention.
    • EMBODIMENTS
  • In order to facilitate the understanding of the present invention, a known kind of delay-locked loop (DLL) circuit 100 is shown in FIG. 1. The circuit 100 in FIG. 1 comprises first input means 110 for an input signal, Vin, which input means split the input signal into a first and a second input branch.
  • The signal in the first input branch of the DLL-circuit is input to a tunable delay component 120, which component thus also has an input possibility for the input of a control or tuning signal, said control signal controlling the delay to which the input signal Vin is exposed.
  • The output from the delay component 120 is split into a first and a second output branch, where the first output branch is used as an output signal from the DLL-circuit, the signal having the desired delay.
  • The signal in the second output branch from the delay component 120 is used as one of two input signals to a phase detector 150.
  • The signal in the second input branch of the DLL is used as the other of the two input signals to the phase detector 150. Thus, the phase detector serves to detect the phase difference or delay between the non-delayed signal and the output signal from the delay component. The output signal from the phase detector corresponds to the phase difference, and is used as the control signal for the delay component 120 in the first input branch of the DLL-circuit. Suitably, the output signal from the phase detector is passed through a low-pass filter 140 before being input to the delay component 120.
  • The DLL of FIG. 1 can thus provide a phase delay of an input signal, with the phase delay being varied by means of a control signal. However, in contemporary such DLL:s, the most commonly used building block in the delay component are active circuits, usually inverters. The use of, for example, inverters in the DLL will limit the available delays to a certain number of discrete steps.
  • In FIG. 2, a DLL 200 according to the invention is shown, which overcomes this problem of known DLL:s.
  • The DLL 200 of the invention, in similarity to earlier known DLL:s, comprises an input means 210 for a signal Vin which is to be delayed. The input means 210 split the input signal into a first and a second branch, and the signal in the first branch is connected to a component 220 for delaying the signal.
  • As opposed to the conventional DLL 100 shown in FIG. 1, the DLL 200 of the invention makes use of a passive tunable delay line 220 as the delaying component. The detailed function and design of this building block 220 of the DLL 200 will be elaborated upon in more detail below, in connection with FIG. 3.
  • However, one important characteristic of the tunable delay line 220 is that it is possible to tune the delay line so that the electrical distance to be covered by a signal in the line always remains the same, regardless of the frequency of the signal. This means that the phase of a signal entering the delay line 220 will always be the same at a fixed point in the delay line, regardless of the frequency or wavelength of the signal.
  • With renewed reference to FIG. 2, four points with known signal phase have been marked in the delay line 220. The phase at each of these points is known, either by measurement or calculation, and is, by way of example, shown as 90°, 180°, 270° and 360°. As mentioned earlier, the phase at these points will always remain essentially the same, regardless of the wavelength of the input signal, if the delay line is kept properly tuned, which will be explained below.
  • The input signal in the second branch is used as a non-delayed reference for the delay caused by the tuning line in the first branch, which is achieved by means of the input signal in the second branch being connected to a means 250 for phase comparison, in the example shown a phase detector 250. In order to get a second input signal, the phase detector 250 is connected to a point in the delay line with a well defined phase shift, in the example shown 360°.
  • Thus, the two input signals to the phase detector are the non-delayed signal from the first branch, and the signal from the second branch which has been shifted 360°. The phase difference between these two signals should accordingly be zero, resulting in an output signal from the phase detector which corresponds to zero phase difference. The output signal from the phase detector 250 is used as a reference signal or control signal for controlling the tunable delay line 220, preferably after having been passed through a low pass filter 240.
  • The filtered output signal from the phase detector 250 is then used as input to a control means 230 for controlling the electrical distance which a signal passing through the delay line will have to cover. In this way, the electrical distance can be kept at a constant and desired value, regardless of the wavelength of the input signal Vin.
  • It should be emphasized again that the phase delays shown in FIG. 2 and mentioned above are only examples, any phase difference can be obtained from the DLL 200 by accessing the proper points in the delay line.
  • As for the function of the filter 240, it could be mentioned that its function is an integrating one.
  • In addition, the phase detector 250 could in an alternative embodiment compare with another phase position than 360 degrees.
  • In FIG. 3, a tunable delay line 220 as used in FIG. 2 is shown in more detail: as mentioned previously, the delay line 220 is preferably a tunable ferroelectric delay line. Such a delay line can consist of the components shown in FIG. 3: an electrical conductor 305 is supported by a dielectric material 310 which is a ferroelectric material. The ferroelectric material in turn rests on a ground plane 315. The control signal to the control means 230 shown in FIG. 2 is connected so that it applies a voltage, VTUNE between the conductor 305 and the ground plane 315, thereby altering the dielectric constant ε of the material 310, which causes the electrical distance to be covered by a wave through the component 220 to vary as desired.
  • Suitably, the control signal, VTUNE, is applied to the conductor via an electrical component such as a resistor or an inductance. This is in order to provide high impedance for the signal, but to simultaneously let through a DC or low frequency bias voltage.
  • Some advantages of the invention that might be mentioned are the following:
      • Since the circuit of the invention is passive, it doesn't interfere with the input signal, thus offering the possibility of using a modulated input signal.
      • As a passive circuit, it doesn't consume power.
      • The circuit of the invention offers a wide tuning range.
      • The phase delay offered by the circuit of the invention can be chosen more or less arbitrarily, and changed over a continuous range.

Claims (5)

1. A delay-locked loop circuit, comprising input means for a signal that is to be delayed, said input means comprising means for splitting said input signal into a first and a second branch, where the signal in the first branch is connected to a component for delaying the signal and the signal in the second branch is used as a non-delayed reference for the delay caused by the delay component in the first branch, characterized in that the delay component is a passive tunable delay line, with the circuit comprising tuning means for the tunable delay line, said tuning means being affected by said reference signal, and with the first branch comprising output means for outputting a delayed signal with a chosen phase delay.
2. The circuit of claim 1, in which the delay component is continuously tunable.
3. The circuit of claim 1, in which the delay component is a passive component.
4. The circuit of claim 1, in which the delay component is a tunable ferroelectric delay line.
5. The circuit of claim 1, in which the second branch comprises a phase detector, by means of which the non-delayed signal of the second branch is compared to the delayed signal in the first branch at a point in the first branch where the delay to be caused by the delay component is known, the output signal from the phase detector being used as a control signal for the tuning means for the delay component of the first branch.
US10/581,786 2003-12-10 2003-12-10 Delay locked loop with precision controlled delay Expired - Fee Related US7456664B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SE2003/001918 WO2005057718A1 (en) 2003-12-10 2003-12-10 A delay-locked loop with precision controlled delay

Publications (2)

Publication Number Publication Date
US20070139089A1 true US20070139089A1 (en) 2007-06-21
US7456664B2 US7456664B2 (en) 2008-11-25

Family

ID=34676085

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/581,786 Expired - Fee Related US7456664B2 (en) 2003-12-10 2003-12-10 Delay locked loop with precision controlled delay

Country Status (9)

Country Link
US (1) US7456664B2 (en)
EP (1) EP1692740B1 (en)
JP (1) JP2007521702A (en)
KR (1) KR101101050B1 (en)
CN (1) CN1879252B (en)
AT (1) ATE488912T1 (en)
AU (1) AU2003304613A1 (en)
DE (1) DE60335043D1 (en)
WO (1) WO2005057718A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9660625B1 (en) 2016-05-03 2017-05-23 International Business Machines Corporation Continuously tunable delay line
US11226649B2 (en) 2018-01-11 2022-01-18 Nxp B.V. Clock delay circuit
CN111158635B (en) * 2019-12-27 2021-11-19 浙江大学 FeFET-based nonvolatile low-power-consumption multiplier and operation method thereof

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3768046A (en) * 1972-05-12 1973-10-23 H Lorber Precision distributed parameter delay line
US5679624A (en) * 1995-02-24 1997-10-21 Das; Satyendranath High Tc superconductive KTN ferroelectric time delay device
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US6350335B1 (en) * 1999-02-16 2002-02-26 Lucent Technologies Inc. Microstrip phase shifters
US6396338B1 (en) * 1999-10-26 2002-05-28 Trw Inc. Variable delay line detector
US20020140471A1 (en) * 2001-03-30 2002-10-03 Fiscus Timothy E. Pre-divider architecture for low power in a digital delay locked loop
US20030067334A1 (en) * 2001-10-05 2003-04-10 Eckhard Brass Circuit configuration for processing data, and method for identifying an operating state
US20030099321A1 (en) * 2001-11-02 2003-05-29 Jui-Kuo Juan Cascaded delay locked loop circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999043036A1 (en) * 1998-02-20 1999-08-26 Sumitomo Electric Industries, Ltd. Phase shifter and scanning antenna
JPH11239002A (en) 1998-02-20 1999-08-31 Sumitomo Electric Ind Ltd Phase shifter

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3768046A (en) * 1972-05-12 1973-10-23 H Lorber Precision distributed parameter delay line
US5679624A (en) * 1995-02-24 1997-10-21 Das; Satyendranath High Tc superconductive KTN ferroelectric time delay device
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US6350335B1 (en) * 1999-02-16 2002-02-26 Lucent Technologies Inc. Microstrip phase shifters
US6396338B1 (en) * 1999-10-26 2002-05-28 Trw Inc. Variable delay line detector
US20020140471A1 (en) * 2001-03-30 2002-10-03 Fiscus Timothy E. Pre-divider architecture for low power in a digital delay locked loop
US20030067334A1 (en) * 2001-10-05 2003-04-10 Eckhard Brass Circuit configuration for processing data, and method for identifying an operating state
US20030099321A1 (en) * 2001-11-02 2003-05-29 Jui-Kuo Juan Cascaded delay locked loop circuit
US7154978B2 (en) * 2001-11-02 2006-12-26 Motorola, Inc. Cascaded delay locked loop circuit

Also Published As

Publication number Publication date
WO2005057718A1 (en) 2005-06-23
AU2003304613A1 (en) 2005-06-29
EP1692740A1 (en) 2006-08-23
KR20060111563A (en) 2006-10-27
CN1879252B (en) 2012-07-18
CN1879252A (en) 2006-12-13
ATE488912T1 (en) 2010-12-15
JP2007521702A (en) 2007-08-02
KR101101050B1 (en) 2011-12-29
EP1692740B1 (en) 2010-11-17
US7456664B2 (en) 2008-11-25
DE60335043D1 (en) 2010-12-30

Similar Documents

Publication Publication Date Title
US4785253A (en) Integrated electric filter with adjustable RC parameters
US4980653A (en) Phase locked loop
US6549599B2 (en) Stable phase locked loop having separated pole
US8610474B2 (en) Signal distribution networks and related methods
WO2001001577A8 (en) Adjustable bandwidth phase locked loop with fast settling time
EP0908013B1 (en) Delay circuit and method
EP0563945A1 (en) Phase locked loop
US7456664B2 (en) Delay locked loop with precision controlled delay
US4463321A (en) Delay line controlled frequency synthesizer
CA2545983C (en) An oscillator circuit with tuneable signal delay means
EP1006660A2 (en) Clock reproduction and identification apparatus
EP0863615A1 (en) Frequency tracking arrangements
KR19990080891A (en) Phase lock frequency synthesizer with multiple bands
EP0565325B1 (en) AFC circuit and IC of the same
CN1117667A (en) Switched Capacitor Bandpass Filter for Detecting Indicator Signals
KR100272524B1 (en) Charge pump phase lock loop
US20200106450A1 (en) Multi-phase clock generation circuit
US6654899B2 (en) Tracking bin split technique
Shreve et al. Surface Acoustic Wave Devices for Use in a High Performance Television Tuner
US7054172B2 (en) Method and structure for active power supply control and stabilization
KR950003115Y1 (en) Frequency generator
JPH09200046A (en) Phase difference control pll circuit
Pinac et al. A Hybrid Integrated Circuit Microwave Telemetry Transmitter and Command Receiver
SU1095359A1 (en) Device for automatic tuning of oscillatory circuit
JPS60189327A (en) Pll circuit

Legal Events

Date Code Title Description
AS Assignment

Owner name: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL), SWEDEN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JACOBSSON, HARALD;GEVORGIAN, SPARTAK;LEWIN, THOMAS;REEL/FRAME:017987/0031;SIGNING DATES FROM 20060426 TO 20060427

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: HIGHBRIDGE PRINCIPAL STRATEGIES, LLC (AS COLLATERA

Free format text: LIEN;ASSIGNOR:OPTIS CELLULAR TECHNOLOGY, LLC;REEL/FRAME:031866/0697

Effective date: 20131219

AS Assignment

Owner name: WILMINGTON TRUST, NATIONAL ASSOCIATION (AS COLLATE

Free format text: SECURITY AGREEMENT;ASSIGNOR:OPTIS CELLULAR TECHNOLOGY, LLC;REEL/FRAME:032167/0406

Effective date: 20131219

AS Assignment

Owner name: CLUSTER LLC, DELAWARE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TELEFONAKTIEBOLAGET L M ERICSSON (PUBL);REEL/FRAME:032326/0219

Effective date: 20131219

Owner name: OPTIS CELLULAR TECHNOLOGY, LLC, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CLUSTER LLC;REEL/FRAME:032326/0402

Effective date: 20131219

AS Assignment

Owner name: HIGHBRIDGE PRINCIPAL STRATEGIES, LLC, AS COLLATERA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OPTIS CELLULAR TECHNOLOGY, LLC;REEL/FRAME:032786/0546

Effective date: 20140424

AS Assignment

Owner name: HIGHBRIDGE PRINCIPAL STRATEGIES, LLC, AS COLLATERA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE TO READ "SECURITY INTEREST" PREVIOUSLY RECORDED ON REEL 032786 FRAME 0546. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:OPTIS CELLULAR TECHNOLOGY, LLC;REEL/FRAME:033281/0216

Effective date: 20140424

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: OPTIS CELLULAR TECHNOLOGY, LLC, TEXAS

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:HPS INVESTMENT PARTNERS, LLC;REEL/FRAME:039359/0916

Effective date: 20160711

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20201125

OSZAR »