US5045495A - Forming twin wells in semiconductor devices - Google Patents

Forming twin wells in semiconductor devices Download PDF

Info

Publication number
US5045495A
US5045495A US07/502,532 US50253290A US5045495A US 5045495 A US5045495 A US 5045495A US 50253290 A US50253290 A US 50253290A US 5045495 A US5045495 A US 5045495A
Authority
US
United States
Prior art keywords
oxide layer
conductivity type
substrate
dopant
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US07/502,532
Inventor
Martin J. Teague
Andrew D. Strachan
Martin A. Henry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
STMicroelectronics lnc USA
Original Assignee
Inmos Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=10654649&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US5045495(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Inmos Ltd filed Critical Inmos Ltd
Assigned to INMOS LIMITED, A CORP. OF THE UNITED KINGDOM reassignment INMOS LIMITED, A CORP. OF THE UNITED KINGDOM ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: HENRY, MARTIN A., STRACHAN, ANDREW D., TEAGUE, MARTIN J.
Priority to CA 2034109 priority Critical patent/CA2034109A1/en
Application granted granted Critical
Publication of US5045495A publication Critical patent/US5045495A/en
Assigned to SGS-THOMSON MICROELECTRONICS LIMITED reassignment SGS-THOMSON MICROELECTRONICS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INMOS LIMITED
Assigned to ST MICROELECTRONICS, INC., A DELAWARE CORPORATION reassignment ST MICROELECTRONICS, INC., A DELAWARE CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STMICROELECTRONICS LIMITED, A CORP., ORG. UNDER THE LAWS OF ENGLAND
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
    • H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
    • H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos

Definitions

  • the present invention relates to a method of forming a well of one conductivity type in a silicon substrate.
  • the present invention relates to a method for forming twin wells in a CMOS structure.
  • CMOS semiconductor devices at the well boundary there is a step height difference between N-wells and P-wells in the standard twin-well scheme which is generally around 2000 Angstroms.
  • the step height can lead to variations in photoresist thickness in the region up to 10 micrometers wide on either side of the boundary. Due to standing wave effects which occur during photolithographic exposure of the photoresist, each variation of about 600 Angstroms, when mercury G-line exposure tools are employed, in the photoresist thickness can cause variations between the designed dimensions and the actually printed dimensions of up to 0.15 um.
  • the present invention provides a method of forming a well of one conductivity type in a silicon substrate, which method comprises the steps of:
  • FIG. 1 shows a section through a silicon wafer structure after growth of a layer of oxide, deposition of a layer of silicon nitride, application of a patterned photoresist, etching of exposed silicon nitride and subsequent implantation of a dopant;
  • FIG. 2 shows the structure of FIG. 1 after the photoresist has been removed and after further growth of the oxide layer
  • FIG. 3 shows the structure of FIG. 2 after removal of the silicon nitride and during implantation of a dopant
  • FIG. 4 shows the structure of FIG. 3 after oxidation of the structure
  • FIG. 5 shows the structure of FIG. 4 after well drive-in
  • FIG. 6 shows the structure of FIG. 5 after removal of the oxide.
  • a silicon wafer substrate 2 is initially oxidized in a known manner in order to grow thereon an oxide layer 4 which is around 500 Angstroms thick.
  • a silicon nitride (Si3N4) layer 6 about 1000 Angstroms thick is then deposited over the oxide layer by chemical vapour deposition.
  • the combined oxide and nitride layers 4, 6 are then patterned with a photoresist layer 8 and the structure is then etched in a conventional manner leaving the photoresist 8 in place and exposing an area 10 of the silicon which is covered by a residual layer 11 of about 350 Angstroms of the initial oxide layer 4 and which is intended to define the well which is subsequently to be formed.
  • a dopant 12 of one conductivity type is implanted into the area 10, the implant 12 ultimately being employed to define the well which is formed.
  • the implant is typically 2.7 ⁇ 10 12 ions/cm 2 boron at 125 keV (per ion).
  • the resultant structure is shown in FIG. 1 and the steps employed to form the structure of FIG. 1 are conventional.
  • the dopant implant 12 is a P-dopant implant since a P-well is designed to be formed.
  • the method described can readily be modified, as the man skilled in the art would readily appreciate, to provide a counterdoped N-well and a P-pseudowell on a P-type substrate.
  • the photoresist layer 8 is then removed and a masking oxide 14 about 3000 Angstroms thick is then grown e.g. by a known thermal process in the area 10 above the implant 12.
  • the masking oxide 14 is thinner than masking oxide produced by the conventional process for forming twin wells which has a thickness of around 4000 to 5000 Angstroms and the significance of this thickness difference is discussed hereinbelow.
  • the silicon nitride layer 6 is then removed, e.g. by hot orthophosphoric acid, leaving about 500 Angstroms of initial oxide over those areas to form the N-pseudowell and about 3000 Angstroms of masking oxide over the area 10 to form the P-well.
  • a dopant of opposite conductivity type to the dopant implant 12 is then implanted into the region 16 of the substrate 2 which surrounds the region 10 in the illustrated embodiment, the region 16 being implanted with an N-dopant e.g. phosphorous which is intended to define the N-pseudowell adjacent to the P-well.
  • the N-dopant is implanted through those portions of the original oxide layer 4 which are adjacent the masking oxide 14.
  • the masking oxide 14 prevents N-dopant implantation into the area 10 of the substrate which lies thereunder.
  • the dose of the N-pseudowell implant is the same as that of the conventional process for making twin wells, for example 3.7 ⁇ 10 12 ions/cm 2 phosphorous, but the energy of the implant is reduced compared to the known process from about 120 keV to 60 keV (per ion) in order to preclude implant penetration through the thinner masking oxide 14 used in the present invention.
  • the N-implant 18 which is intended to define the N-pseudowell surrounds the P-implant 12 which is intended to define the P-well.
  • the next steps in the method of the present invention are to activate and drive in the implanted species, this being known as well drive-in, and to oxidize the substrate to reduce the height of the step 20 between the masking oxide 14 and the remaining portions of the original oxide layer 4.
  • the well drive-in step and the oxidation step may be carried out either as a one step process or as a two step process having consecutive steps in any order.
  • the well drive-in and oxidation steps are carried out in a one step process and this particular process is described below.
  • FIG. 4 shows the substrate after oxidation
  • FIG. 5 shows the substrate after subsequent well drive-in although it will be appreciated that in the following description oxidation and well drive-in occur simultaneously.
  • the oxidation step before the well drive-in during the one step process is carried out by heating the substrate in a steam ambient atmosphere in which hydrogen and oxygen have been introduced (to produce a steam/oxygen atmosphere) for a predetermined period of time during the cycle.
  • the well drive-in is then completed by switching the gases to an inert ambient atmosphere, which is typically nitrogen. This accordingly keeps the temperature cycle the same for both steps; typically the temperature is around 1200° C.
  • Steam is employed to minimize the time of the oxidation step, although a dry oxidation could be used if desired.
  • the step height 20 between the masking oxide 14 and the original oxide layer 4 is greatly reduced since the oxide layer 4 grows much quicker in relation to the growth of the masking oxide 14.
  • the oxidation by means of steam and oxygen is carried out for around 30 minutes to give a final step height 20 between the upper surfaces of two oxide layers 4, 14 of around 400 Angstroms. Oxidation steps longer than about 60 minutes are not suitable unless changes to well implant doses are employed in order to compensate for dopant segregation. This may also lead to stacking faults being created in the oxide. It would be understood by the skilled man that since the step height 20 on the surface of the oxide layers 4, 14 is reduced to around 400 Angstroms, then the corresponding step height 22 at the silicon/oxide interface (which ultimately consitutes the step height 22 at the well boundary) is similarly reduced to around 400 Angstroms due to the mechanism of the growth of the oxide on the silicon.
  • the implanted dopants 12 and 18 are activated and diffuse into the silicon substrate to define a P-well 24 which is surrounded by an N-pseudowell 26. The resultant structure is shown in FIG. 5.
  • the last step in the well formation is to remove all of the oxide constituted by the masking oxide 14 and the remaining portions of the original oxide layer 4 e.g. by means of a 10:1 H 2 O: HF dip.
  • the final well structure is shown in FIG. 6. It will be seen that there is a step height 22 of around 400 Angstroms at the boundary between the surface of the well region 28 and the adjacent silicon surface 30.
  • Conventional CMOS process steps may subsequently be used in order to form CMOS semiconductor devices.
  • the well boundary step height is around 400 Angstroms and this compares with the height of around 2000 Angstroms for the conventional well-forming process.
  • the present invention has provided a solution to the aforementioned problems of the prior art by minimizing the topography variations at the well boundary.
  • the region where linewidths are affected by the well step has been reduced from 10 microns on either side of the boundary to 2 microns on either side of the boundary.
  • the linewidth variation within the affected region has been reduced from 0.15 microns to less than 0.05 microns.
  • Such an improvement is more than sufficient to allow critical circuitry to be placed as little as 2 microns from the well edge. This can offer very substantial area savings over the prior art, particularly in some circuit applications such as full CMOS (6 transistor) static random access memory (SRAM) cells.
  • the present inventors have also discovered that the presence of a 400 Angstrom step is sufficient to secure adequate contrast for darkfield alignment of subsequent layers in photolithographic steps.
  • the present invention also provides the further processing advantage in that by reducing the well step to around 400 Angstroms compared to the prior art value of around 2000 Angstroms, large scale topography variations associated with conventional twin well CMOS structures are removed and this can considerably simplify the process for obtaining planarization of the structure which will improve both device yield and circuit reliability.
  • a further advantage of the present invention is that the process is a modification of the standard self-aligned twin-well method which does not require any additional process steps to improve device shrinkability and reliability.
  • a masking oxide 4000 to 5000 Angstroms thick was grown on the substrate.
  • This particular oxide thickness has hitherto been employed in order to ensure no penetration of the P-well by N-dopant (i.e. phosphorous) which has been pushed out of the oxide during the well drive-in.
  • N-dopant i.e. phosphorous
  • the present inventors have discovered that a 3000 Angstrom thick masking oxide is easily sufficient to prevent this effect, and by consuming less of the substrate, minimizes the step height to be reduced during the well drive-in.
  • the conventional practice has been to dip off about 3000 Angstroms of the masking oxide in order to remove the implanted N-dopant (i.e. phosphorous) from the oxide above the P-well, again this being done to guard against N-dopant push out from the oxide during the well drive-in.
  • N-dopant i.e. phosphorous
  • the phosphorous present in the oxide cannot segregate out into the P-well because the diffusion coefficient of the phosphorous with respect of the oxidizing species is at least several orders of magnitude less at the well drive-in temperature (around 1200° C.), and hence the oxidation front develops much faster than the phosphorous can diffuse to the interface and segregate out.
  • the present invention offers the further advantage that the conventional dipping step before well drive-in can be omitted.
  • the present invention provides a method of repeatably controlling the step height between N- and P- wells to a minimum value so as still to ensure adequate contrast for darkfield alignment of subsequent layers but so as to reduce the variation in photoresist thickness at the well boundary to enable optimization of the use of the silicon surface.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

A method of forming a well of one conductivity type in a silicon substrate having a first surface region thereof which is doped with a dopant of one conductivity type and a second surface region thereof which is doped with a dopant of opposite conductivity type. The first and second regions are covered by respective first and second portions of an oxide layer which has been grown on the silicon substrate, the first portion being thicker than the second portion. The substrate is oxidized thereby to increase the thickness of the oxide layer such that the difference in thickness between the first and second portions is reduced. The substrate is also heated to cause diffusion of the dopant of one conductivity type thereby to form a well and of the dopant of opposite conductivity type down into the substrate. The heating step is carried out before, during or after the oxidizing step. The oxide layer is then removed thereby to expose the substrate surface which has a step of around 400 Angstroms in the region of the well boundary.

Description

BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a well of one conductivity type in a silicon substrate. In particular, the present invention relates to a method for forming twin wells in a CMOS structure.
In conventional CMOS semiconductor devices, at the well boundary there is a step height difference between N-wells and P-wells in the standard twin-well scheme which is generally around 2000 Angstroms. When a photoresist layer is applied over the well boundary between the twin wells, the step height can lead to variations in photoresist thickness in the region up to 10 micrometers wide on either side of the boundary. Due to standing wave effects which occur during photolithographic exposure of the photoresist, each variation of about 600 Angstroms, when mercury G-line exposure tools are employed, in the photoresist thickness can cause variations between the designed dimensions and the actually printed dimensions of up to 0.15 um. Until recently, this loss of dimensional control close to the well boundaries has not been of great significance since such variations accounted for less than 10% of the total designed linewidth (10% being a typical allowable design tolerance). However, linewidths are now being reduced to levels where a 0.15 um variation could account for over 15% of the total feature dimension. Such linewidth variation would effectively exclude critical circuits from within a region 10 microns wide on either side of the well boundary. Hitherto, this restriction on the critical circuit placement has not been a serious design handicap because of the well known bulk CMOS latch-up phenomenon, which itself has precluded placement of active circuitry close to the well boundaries.
However, with the availability of epitaxial silicon substrates and other developments in CMOS latch-up suppression, it has become possible to reduce the spacing between N- and P-channel sources and drains across the well boundary from around 12 microns to less than 4 microns. In order to be able fully to benefit from the advances in CMOS latch-up suppression, there is a real technical need for linewidth variations associated with the well boundaries to be reduced in order to allow the area adjacent to (i.e. within 2 to 10 microns from) the well boundaries to be fully utilized.
In addition, the presence of a step height difference at the well boundary of around 2000 Angstroms in known devices reduces the planarity of the devices. Modern VLSI devices are becoming increasingly reliant on multiple interconnect levels in order to achieve performance, functionality and reliability goals. All such schemes rely heavily on excellent planarization of the dielectric layers between the interconnect levels. Thus there is a continual technical need to increase the overall device planarity.
SUMMARY OF THE INVENTION
The present invention provides a method of forming a well of one conductivity type in a silicon substrate, which method comprises the steps of:
(a) providing a silicon substrate having a first surface region thereof which is doped with a dopant of one conductivity type and a second surface region thereof which is doped with a dopant of opposite conductivity type, the first and second regions being covered by respective first and second portions of an oxide layer which has been grown on the silicon substrate, the first portion being thicker than the second portion;
(b) oxidizing the substrate thereby to increase the thickness of the oxide layer such that the difference in thickness between the first and second portions is reduced;
(c) heating the substrate to cause diffusion the said dopant of one conductivity type thereby to form a well of said one conductivity type in the substrate and also diffusion of the said dopant of opposite conductivity type down into the substrate, the heating step being carried out before, during or after oxidizing step (b); and
(d) removing the oxide layer thereby to expose the substrate surface which has a step in the region of the well boundary.
BRIEF DESCRIPTION OF THE DRAWINGS
An embodiment of the present invention will now be described by way of example only with reference to the accompanying drawings in which:
FIG. 1 shows a section through a silicon wafer structure after growth of a layer of oxide, deposition of a layer of silicon nitride, application of a patterned photoresist, etching of exposed silicon nitride and subsequent implantation of a dopant;
FIG. 2 shows the structure of FIG. 1 after the photoresist has been removed and after further growth of the oxide layer;
FIG. 3 shows the structure of FIG. 2 after removal of the silicon nitride and during implantation of a dopant;
FIG. 4 shows the structure of FIG. 3 after oxidation of the structure;
FIG. 5 shows the structure of FIG. 4 after well drive-in; and
FIG. 6 shows the structure of FIG. 5 after removal of the oxide.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 1, a silicon wafer substrate 2 is initially oxidized in a known manner in order to grow thereon an oxide layer 4 which is around 500 Angstroms thick. A silicon nitride (Si3N4) layer 6 about 1000 Angstroms thick is then deposited over the oxide layer by chemical vapour deposition. The combined oxide and nitride layers 4, 6 are then patterned with a photoresist layer 8 and the structure is then etched in a conventional manner leaving the photoresist 8 in place and exposing an area 10 of the silicon which is covered by a residual layer 11 of about 350 Angstroms of the initial oxide layer 4 and which is intended to define the well which is subsequently to be formed. Subsequently, a dopant 12 of one conductivity type is implanted into the area 10, the implant 12 ultimately being employed to define the well which is formed. The implant is typically 2.7×1012 ions/cm2 boron at 125 keV (per ion). The resultant structure is shown in FIG. 1 and the steps employed to form the structure of FIG. 1 are conventional.
In the following description, there is described a twin-well process with a counterdoped P-well and an N-pseudowell on an N-type silicon substrate. Accordingly, the dopant implant 12 is a P-dopant implant since a P-well is designed to be formed. However, the method described can readily be modified, as the man skilled in the art would readily appreciate, to provide a counterdoped N-well and a P-pseudowell on a P-type substrate.
Referring now to FIG. 2, the photoresist layer 8 is then removed and a masking oxide 14 about 3000 Angstroms thick is then grown e.g. by a known thermal process in the area 10 above the implant 12. The masking oxide 14 is thinner than masking oxide produced by the conventional process for forming twin wells which has a thickness of around 4000 to 5000 Angstroms and the significance of this thickness difference is discussed hereinbelow.
Referring to FIG. 3, the silicon nitride layer 6 is then removed, e.g. by hot orthophosphoric acid, leaving about 500 Angstroms of initial oxide over those areas to form the N-pseudowell and about 3000 Angstroms of masking oxide over the area 10 to form the P-well. A dopant of opposite conductivity type to the dopant implant 12 is then implanted into the region 16 of the substrate 2 which surrounds the region 10 in the illustrated embodiment, the region 16 being implanted with an N-dopant e.g. phosphorous which is intended to define the N-pseudowell adjacent to the P-well. The N-dopant is implanted through those portions of the original oxide layer 4 which are adjacent the masking oxide 14. The masking oxide 14 prevents N-dopant implantation into the area 10 of the substrate which lies thereunder. The dose of the N-pseudowell implant is the same as that of the conventional process for making twin wells, for example 3.7×1012 ions/cm2 phosphorous, but the energy of the implant is reduced compared to the known process from about 120 keV to 60 keV (per ion) in order to preclude implant penetration through the thinner masking oxide 14 used in the present invention.
Referring to FIG. 4, it may be seen that the N-implant 18 which is intended to define the N-pseudowell surrounds the P-implant 12 which is intended to define the P-well.
The next steps in the method of the present invention are to activate and drive in the implanted species, this being known as well drive-in, and to oxidize the substrate to reduce the height of the step 20 between the masking oxide 14 and the remaining portions of the original oxide layer 4. The well drive-in step and the oxidation step may be carried out either as a one step process or as a two step process having consecutive steps in any order. In a particularly preferred arrangement, the well drive-in and oxidation steps are carried out in a one step process and this particular process is described below. However, for the sake of clarity of illustration, FIG. 4 shows the substrate after oxidation and FIG. 5 shows the substrate after subsequent well drive-in although it will be appreciated that in the following description oxidation and well drive-in occur simultaneously.
In the preferred method, the oxidation step before the well drive-in during the one step process is carried out by heating the substrate in a steam ambient atmosphere in which hydrogen and oxygen have been introduced (to produce a steam/oxygen atmosphere) for a predetermined period of time during the cycle. The well drive-in is then completed by switching the gases to an inert ambient atmosphere, which is typically nitrogen. This accordingly keeps the temperature cycle the same for both steps; typically the temperature is around 1200° C. Steam is employed to minimize the time of the oxidation step, although a dry oxidation could be used if desired. In the oxidation process, the step height 20 between the masking oxide 14 and the original oxide layer 4 is greatly reduced since the oxide layer 4 grows much quicker in relation to the growth of the masking oxide 14. This growth rate difference is present since the oxidation rate decreases as the thickness of oxide increases. Therefore the oxidation rate in the N-pseudowell region where the oxide layer 4 is around 500 Angstroms thick is initially much higher than in the P-well region where the masking oxide is around 3000 Angstroms thick. This gives an initial reduction in silicon step height although the advantage of diffusion rate limitation decreases as the thickness of oxide in the N-pseudowell region increases. Subsequent oxidation of the silicon after this initial step is still continued at a slightly higher rate in the N-pseudowell region because the N-doping (i.e. by phosphorous) accelerates the oxidation relative to the P-doping (i.e. by boron). In the preferred process, the oxidation by means of steam and oxygen is carried out for around 30 minutes to give a final step height 20 between the upper surfaces of two oxide layers 4, 14 of around 400 Angstroms. Oxidation steps longer than about 60 minutes are not suitable unless changes to well implant doses are employed in order to compensate for dopant segregation. This may also lead to stacking faults being created in the oxide. It would be understood by the skilled man that since the step height 20 on the surface of the oxide layers 4, 14 is reduced to around 400 Angstroms, then the corresponding step height 22 at the silicon/oxide interface (which ultimately consitutes the step height 22 at the well boundary) is similarly reduced to around 400 Angstroms due to the mechanism of the growth of the oxide on the silicon. In the well drive-in step, the implanted dopants 12 and 18 are activated and diffuse into the silicon substrate to define a P-well 24 which is surrounded by an N-pseudowell 26. The resultant structure is shown in FIG. 5.
Referring to FIG. 6, the last step in the well formation is to remove all of the oxide constituted by the masking oxide 14 and the remaining portions of the original oxide layer 4 e.g. by means of a 10:1 H2 O: HF dip. The final well structure is shown in FIG. 6. It will be seen that there is a step height 22 of around 400 Angstroms at the boundary between the surface of the well region 28 and the adjacent silicon surface 30. Conventional CMOS process steps may subsequently be used in order to form CMOS semiconductor devices.
It will be seen from FIG. 6 that after the oxide has been removed the well boundary step height is around 400 Angstroms and this compares with the height of around 2000 Angstroms for the conventional well-forming process. Thus the present invention has provided a solution to the aforementioned problems of the prior art by minimizing the topography variations at the well boundary. With a 400 Angstrom step at the well boundary, the region where linewidths are affected by the well step has been reduced from 10 microns on either side of the boundary to 2 microns on either side of the boundary. In addition, the linewidth variation within the affected region has been reduced from 0.15 microns to less than 0.05 microns. Such an improvement is more than sufficient to allow critical circuitry to be placed as little as 2 microns from the well edge. This can offer very substantial area savings over the prior art, particularly in some circuit applications such as full CMOS (6 transistor) static random access memory (SRAM) cells.
The present inventors have also discovered that the presence of a 400 Angstrom step is sufficient to secure adequate contrast for darkfield alignment of subsequent layers in photolithographic steps.
The present invention also provides the further processing advantage in that by reducing the well step to around 400 Angstroms compared to the prior art value of around 2000 Angstroms, large scale topography variations associated with conventional twin well CMOS structures are removed and this can considerably simplify the process for obtaining planarization of the structure which will improve both device yield and circuit reliability.
A further advantage of the present invention is that the process is a modification of the standard self-aligned twin-well method which does not require any additional process steps to improve device shrinkability and reliability.
In the known method, as described above a masking oxide 4000 to 5000 Angstroms thick was grown on the substrate. This particular oxide thickness has hitherto been employed in order to ensure no penetration of the P-well by N-dopant (i.e. phosphorous) which has been pushed out of the oxide during the well drive-in. In fact, the present inventors have discovered that a 3000 Angstrom thick masking oxide is easily sufficient to prevent this effect, and by consuming less of the substrate, minimizes the step height to be reduced during the well drive-in.
Furthermore, in the known process, after the implantation of the dopant to form the pseudowell (i.e. by the corresponding implantation step shown in FIG. 3), the conventional practice has been to dip off about 3000 Angstroms of the masking oxide in order to remove the implanted N-dopant (i.e. phosphorous) from the oxide above the P-well, again this being done to guard against N-dopant push out from the oxide during the well drive-in. In the present invention, since an oxidation step is added to the well drive-in step, the phosphorous present in the oxide cannot segregate out into the P-well because the diffusion coefficient of the phosphorous with respect of the oxidizing species is at least several orders of magnitude less at the well drive-in temperature (around 1200° C.), and hence the oxidation front develops much faster than the phosphorous can diffuse to the interface and segregate out. Thus the present invention offers the further advantage that the conventional dipping step before well drive-in can be omitted.
The present invention provides a method of repeatably controlling the step height between N- and P- wells to a minimum value so as still to ensure adequate contrast for darkfield alignment of subsequent layers but so as to reduce the variation in photoresist thickness at the well boundary to enable optimization of the use of the silicon surface.

Claims (20)

What we claim is:
1. A method of forming a well of one conductivity type in a silicon substrate, which method comprises the steps of:
(a) providing a silicon substrate having a first surface region thereof which is doped with a dopant of one conductivity type and a second surface region thereof which is doped with a dopant of opposite conductivity type, the first and second regions being covered by respective first and second portions of an oxide layer which has been grown on the silicon substrate, the first portion being thicker than the second portion;
(b) oxidizing the substrate thereby to increase the thickness of the oxide layer such that the difference in thickness between the first and second portions is reduced;
(c) heating the substrate to cause diffusion of the said dopant of one conductivity type thereby to form a well of said one conductivity type in the substrate and also diffusion of the said dopant of opposite conductivity type down into the substrate, the heating step being carried out before, during or after oxidizing step (b); and
(d) removing the oxide layer thereby to expose the substrate surface which has a step in the region of the well boundary.
2. A method according to claim 1, wherein the oxidising step (b) and the heating step (c) are carried out as a single step in which the oxidation and heating are performed in different ambient atmospheres.
3. A method according to claim 2 wherein the oxidising and heating steps are carried out at substantially the same temperature.
4. A method according to claim 2 wherein the oxidizing step (b) is carried out by heating the substrate in an oxidising atmosphere at a temperature of around 1200° C.
5. A method according to claim 3 wherein the oxidizing step (b) is carried out by heating the substrate in an oxidising atmosphere at a temperature of around 1200° C.
6. A method according to claim 4 wherein the oxidizing step (b) is carried out for about 30 minutes.
7. A method according to claim 5 wherein the oxidizing step (b) is carried out for about 30 minutes.
8. A method according to claim 1 wherein prior to oxidizing step (b) the first and second portions of the oxide layer have a thickness of around 3000 Angstroms and around 500 Angstroms respectively.
9. A method according to claim 1 wherein the height of the step is around 400 Angstroms.
10. A method according to claim 8 wherein the height of the step is around 400 Angstroms.
11. A method according to claim 1 wherein prior to step (a) the oxide layer is of substantially uniform thickness and the first portion of the oxide layer is formed by masking the second portion of the oxide layer with a masking layer and selectively growing oxide on the first surface region of the silicon substrate.
12. A method according to claim 1 wherein the dopant of opposite conductivity type is implanted into the second surface region of the silicon substrate after formation of the first and second portions of the oxide layer, the first portion of the oxide layer acting to mask the first surface region of the silicon substrate from dopant implantation.
13. A method according to claim 12 wherein the dopant of opposite conductivity type is implanted at an energy of 60 keV per ion.
14. A method according to claim 1 wherein the said second surface region of the silicon substrate is comprised in a pseudowell of opposite conductivity type to that of the said well.
15. A method according to claim 1 wherein the well boundary surrounds the first surface region which is lower than the second surface region.
16. A method of forming a well of one conductivity type in a silicon substrate, which method comprises the steps of:
(a) providing a silicon substrate having a first surface region thereof which is doped with a dopant of one conductivity type and a second surface region thereof which is doped with a dopant of opposite conductivity type, the first and second regions being covered by respective first and second portions of an oxide layer which has been grown on the silicon substrate, the first portion being greater than 800 Angstroms thicker than the second portion;
(b) oxidizing the substrate thereby to increase the thickness of the oxide layer such that the difference in thickness between the first and second portions is reduced to around 800 Angstroms;
(c) heating the substrate to cause diffusion of the said dopant of one conductivity type thereby to form a well of said one conductivity type in the substrate and also diffusion of the said dopant of opposite conductivity type down into the substrate, the heating step being carried out before, during or after oxidizing step (b); and
(d) removing the oxide layer thereby to expose the substrate surface which has a step of around 400 Angstroms in the region of the well boundary.
17. A method according to claim 16, wherein before oxidising step (b) the first portion is around 2500 Angstroms thicker than the second portion.
18. A method according to claim 16 wherein the second portion of the oxide layer is around 500 Angstroms thick.
19. A method according to claim 18 wherein prior to step (a) the oxide layer is of substantially uniform thickness and the first portion of the oxide layer is formed by masking the second portion of the oxide layer with a masking layer and selectively growing oxide on the first surface region of the silicon substrate.
20. A method according to claim 19 wherein the dopant of opposite conductivity type is implanted into the second surface region of the silicon substrate after formation of the first and second portions of the oxide layer, the first portion of the oxide layer acting to mask the first surface region of the silicon substrate from dopant implantation.
US07/502,532 1989-04-07 1990-03-30 Forming twin wells in semiconductor devices Expired - Lifetime US5045495A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA 2034109 CA2034109A1 (en) 1990-03-30 1991-01-14 Drum

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB898907897A GB8907897D0 (en) 1989-04-07 1989-04-07 Forming wells in semiconductor devices
GB8907897 1989-04-07

Publications (1)

Publication Number Publication Date
US5045495A true US5045495A (en) 1991-09-03

Family

ID=10654649

Family Applications (1)

Application Number Title Priority Date Filing Date
US07/502,532 Expired - Lifetime US5045495A (en) 1989-04-07 1990-03-30 Forming twin wells in semiconductor devices

Country Status (5)

Country Link
US (1) US5045495A (en)
EP (1) EP0391561B1 (en)
JP (1) JPH02288359A (en)
DE (1) DE69020772T2 (en)
GB (1) GB8907897D0 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300797A (en) * 1992-03-31 1994-04-05 Sgs-Thomson Microelectronics, Inc. Coplanar twin-well integrated circuit structure
US5364248A (en) * 1992-03-23 1994-11-15 Hitachi, Ltd. Sliding member, a method for producing same, and usages of same
US5661067A (en) * 1995-07-26 1997-08-26 Lg Semicon Co., Ltd. Method for forming twin well
US5946564A (en) * 1997-08-04 1999-08-31 Micron Technology, Inc. Methods of forming integrated circuitry and integrated circuitry
US20050141266A1 (en) * 2003-12-31 2005-06-30 Dongbuanam Semiconductor Inc. Semiconductor device
US20080014708A1 (en) * 2006-07-14 2008-01-17 Samsung Electronics Co., Ltd Method of fabricating semiconductor device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0605965A3 (en) * 1992-12-31 1994-11-02 At & T Corp Method for manufacturing integrated circuits of the CMOS type.
DE69519079T2 (en) * 1994-12-08 2001-03-15 At & T Corp., New York Fabrication of an integrated circuit with twin tubs
KR101008656B1 (en) * 2008-05-22 2011-01-25 한국표준과학연구원 2D dopant imaging spatial resolution reference material
US8153496B1 (en) * 2011-03-07 2012-04-10 Varian Semiconductor Equipment Associates, Inc. Self-aligned process and method for fabrication of high efficiency solar cells

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4027380A (en) * 1974-06-03 1977-06-07 Fairchild Camera And Instrument Corporation Complementary insulated gate field effect transistor structure and process for fabricating the structure
US4516316A (en) * 1984-03-27 1985-05-14 Advanced Micro Devices, Inc. Method of making improved twin wells for CMOS devices by controlling spatial separation
US4554726A (en) * 1984-04-17 1985-11-26 At&T Bell Laboratories CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4442591A (en) * 1982-02-01 1984-04-17 Texas Instruments Incorporated High-voltage CMOS process
US4435895A (en) * 1982-04-05 1984-03-13 Bell Telephone Laboratories, Incorporated Process for forming complementary integrated circuit devices
DE3314450A1 (en) * 1983-04-21 1984-10-25 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING HIGHLY INTEGRATED COMPLEMENTARY MOS FIELD EFFECT TRANSISTOR CIRCUITS

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4027380A (en) * 1974-06-03 1977-06-07 Fairchild Camera And Instrument Corporation Complementary insulated gate field effect transistor structure and process for fabricating the structure
US4516316A (en) * 1984-03-27 1985-05-14 Advanced Micro Devices, Inc. Method of making improved twin wells for CMOS devices by controlling spatial separation
US4554726A (en) * 1984-04-17 1985-11-26 At&T Bell Laboratories CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Wolf et al, Silicon Processing for the VLSI ERA, 1986, pp. 198, 219 220. *
Wolf et al, Silicon Processing for the VLSI ERA, 1986, pp. 198, 219-220.

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5364248A (en) * 1992-03-23 1994-11-15 Hitachi, Ltd. Sliding member, a method for producing same, and usages of same
US5300797A (en) * 1992-03-31 1994-04-05 Sgs-Thomson Microelectronics, Inc. Coplanar twin-well integrated circuit structure
US5661067A (en) * 1995-07-26 1997-08-26 Lg Semicon Co., Ltd. Method for forming twin well
DE19603794B4 (en) * 1995-07-26 2004-06-03 LG Semicon Co., Ltd., Cheongju Method for forming a double well for semiconductor devices
US5946564A (en) * 1997-08-04 1999-08-31 Micron Technology, Inc. Methods of forming integrated circuitry and integrated circuitry
US6215151B1 (en) 1997-08-04 2001-04-10 Micron Technology, Inc. Methods of forming integrated circuitry and integrated circuitry
US20050141266A1 (en) * 2003-12-31 2005-06-30 Dongbuanam Semiconductor Inc. Semiconductor device
US20080014708A1 (en) * 2006-07-14 2008-01-17 Samsung Electronics Co., Ltd Method of fabricating semiconductor device

Also Published As

Publication number Publication date
JPH02288359A (en) 1990-11-28
EP0391561A2 (en) 1990-10-10
DE69020772D1 (en) 1995-08-17
EP0391561B1 (en) 1995-07-12
DE69020772T2 (en) 1995-12-21
EP0391561A3 (en) 1992-01-02
GB8907897D0 (en) 1989-05-24

Similar Documents

Publication Publication Date Title
EP0051488B1 (en) Method for manufacturing a semiconductor device
EP0192668B1 (en) Semiconductor integrated circuits gettered with phosphorus
US4808555A (en) Multiple step formation of conductive material layers
JPS61237422A (en) Manufacturing method of semiconductor device
JPH0832033A (en) Formation of low resistance current path between buried contact and diffusion region and semiconductor device containing such buried contact
US4847213A (en) Process for providing isolation between CMOS devices
CA1287692C (en) Method for manufacturing wells for cmos transistor circuits separated by insulating trenches
US5045495A (en) Forming twin wells in semiconductor devices
US5100830A (en) Method of manufacturing a semiconductor device
EP0417715B1 (en) Method of manufacturing a semicondcutor device
US5229317A (en) Method for preventing out-diffusion of phosphorous and boron in a bpsg-buried trench
US5362670A (en) Semiconductor device producing method requiring only two masks for completion of element isolation regions and P- and N-wells
US20020001972A1 (en) Oxidation of silicon using fluorine implants
EP0561167B1 (en) Semiconductor well structure and method
US5106768A (en) Method for the manufacture of CMOS FET by P+ maskless technique
US4578859A (en) Implant mask reversal process
US5208181A (en) Locos isolation scheme for small geometry or high voltage circuit
EP0284456B1 (en) Pad oxide protect sealed interface isolation process
EP0565936B1 (en) Method of manufacturing a semiconductor well structure
US4409726A (en) Method of making well regions for CMOS devices
JP2843010B2 (en) Method for forming twin well of semiconductor device
US5998843A (en) Semiconductor device with stable threshold voltages
US5946577A (en) Method of manufacturing semiconductor device
US5612247A (en) Method for fabricating isolation region for a semiconductor device
KR0179831B1 (en) Well-forming method of semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: INMOS LIMITED, A CORP. OF THE UNITED KINGDOM, ENGL

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:TEAGUE, MARTIN J.;STRACHAN, ANDREW D.;HENRY, MARTIN A.;REEL/FRAME:005269/0859

Effective date: 19900314

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 4

SULP Surcharge for late payment
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

AS Assignment

Owner name: SGS-THOMSON MICROELECTRONICS LIMITED, UNITED KINGD

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INMOS LIMITED;REEL/FRAME:007662/0508

Effective date: 19960130

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: ST MICROELECTRONICS, INC., A DELAWARE CORPORATION,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS LIMITED, A CORP., ORG. UNDER THE LAWS OF ENGLAND;REEL/FRAME:011190/0101

Effective date: 20000719

FPAY Fee payment

Year of fee payment: 12

OSZAR »