US5945863A - Analog delay circuit - Google Patents

Analog delay circuit Download PDF

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US5945863A
US5945863A US08/878,162 US87816297A US5945863A US 5945863 A US5945863 A US 5945863A US 87816297 A US87816297 A US 87816297A US 5945863 A US5945863 A US 5945863A
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delay
pair
current
differential pair
emitter
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Bruce H. Coy
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MACOM Connectivity Solutions LLC
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Applied Micro Circuits Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator

Definitions

  • the present invention relates to analog delay circuits, and particularly to analog circuits that present an adjustable, or variable, delay between input and output.
  • ⁇ is an integral multiple of a clock T
  • variable delay in a form that can be accommodated in integrated circuit technology is highly desirable, especially in the mixed analog-digital VL,SI technology that is described, for example, by Y. Tsividis in Mixed Analog-Digital VLSI Devices And Technology, (McGraw-Hill, 1996). As Tsividis points out at page 3, mixed analog-digital circuits "help make possible the high performance of the digital systems and circuits themselves". Tsividis at p. 3.
  • the invention is an analog delay circuit that yields a variable delay between an input signal and an output signal, wherein two differential pairs of transistors are connected in parallel, with a first of the differential pairs having a first signal path delay, and a second of the differential pairs having a second signal path delay.
  • the respective delay may be varied by varying a current provided to operate the differential pair.
  • the differential pairs are connected to a current source, preferably embodied as a current digital-to-analog converter ("current DAC") that outputs a pair of complementary currents.
  • a first current of the pair of complementary currents operates the first differential pair, while the second current operates the second differential pair.
  • the current DAC is controlled by a digital code. As the digital code varies, the magnitudes of the complementary currents vary.
  • the delays through the differential pairs vary. Since they operate in parallel, the differential pairs produce a composite variable delay that combines the individual variable delays.
  • the invention therefore yields a current-controlled delay element that may be operated alone, or cascaded with one or more identical delay elements to provide either a variable-length delay line, a current-controlled oscillator with a variable frequency.
  • a further object is to provide an analog delay circuit that may be combined with identical elements to provide a delay line whose total delay may be varied in response to a variable current.
  • Still another object is to provide a current-controlled oscillator with a frequency controlled by a digital code.
  • FIG. 1 is schematic diagram of an analog delay circuit according to this invention
  • FIG. 2 is a representative plot of the complementary currents produced by a current DAC in response to an input digital code
  • FIG. 3 is block diagram of a ring oscillator constructed by cascading multiple delay stages, each of which embodies the analog delay circuit of FIG. 1.
  • FIG. 1 is a schematic diagram of an analog delay circuit according to this invention.
  • the analog delay circuit includes an analog delay element, or delay stage, 8 in combination with a current DAC 14.
  • the delay stage 8 includes a pair of differential transistor pairs 10 and 12.
  • the first differential transistor pair 10 includes emitter-coupled transistors Q1 and Q2, while the second differential pair 12 includes emitter-coupled transistors Q3 and Q4.
  • the two differential pairs are connected to matched pull-up resistors R1 and R2.
  • Each of the pull-up resistors is connected on one side to a collector of a respective transistor in each of the differential pairs 10 and 12, and on its other side to a collector voltage Vcc.
  • resistor R1 is connected to the collectors of transistors Q1 and Q3 and resistor R2 is connected to the collectors of transistors Q2 and Q4. Both resistors R1 and R2 are passive pull-up resistors that bias the transistors to whose collectors they are connected.
  • Each differential pair 10, 12 is essentially an analog amplifier that produces an output signal (OUT) in response to an input signal (IN).
  • Each of the differential pairs 10 and 12 is connected to an output of a current DAC 14.
  • the current DAC 14 is conventional, producing a pair of complementary output currents (Iout/Iout) in response to a digital code input from a register 16.
  • the current Iout sets the differential pair 10 to a level of operation, which may vary between off and full on.
  • the current Iout sets the differential pair 12 to a level of operation between off and full on.
  • the relationship between the digital code and the pair of complementary output currents produced by the current DAC 14 is illustrated in FIG. 2.
  • the digital code may be provided in a digital logic system by way of a data bus 17, or other appropriate means.
  • differential pairs 10 and 12 are connected in parallel between Vcc and the current DAC 14.
  • the delay stage 8 receives the input signal (IN) comprising complementary inputs A/A, and, in response, produces the output (OUT) comprising complementary signals B/B.
  • a delay time between the input and output signals is adjusted according to the composite level at which the two differential pairs 10 and 12 operate.
  • Minimum delay (the fast case) occurs if Iout from the current DAC 14 is full scale, in which circumstance Q3 and Q4 are turned off, while Q1 and Q2 are turned completely on. In this case, the delay is essentially determined by the minimum parametric input values of the transistors Q1 and Q2. As the magnitude of Iout decreases, the response time, and therefore the delay through the differential pair 10 increases.
  • the maximum delay occurs when the magnitude of Iout falls below the level required to keep Q1 and Q2 turned on; in this case, the magnitude of Iout turns Q3 and Q4 fully on.
  • each of the matched resistors Rx and Ry forms a pole with the input capacitance of each of the transistors Q3 and Q4. This added pole in the signal path increases the delay through the differential pair 12 in comparison with that through the differential pair 10. As the magnitude of Iout decreases, the magnitude of Iout increases, and the composite delay through the delay stage 8 decreases.
  • FIG. 3 is a block diagram illustrating a current-controlled ring oscillator comprising delay stages 20, 22, and 24, each identical to the delay stage 8 illustrated in FIG. 1. Adjustment of delay through each of the stages 20, 22 and 24 is provided by a current DAC 30 that produces complementary DAC currents in the manner illustrated in FIGS. 1 and 2. The magnitudes of the complementary currents produced by the current DAC 30 are determined by a digital code registered at 32 and delivered by the data bus 33 in response to circuit operations of a digital logic system. With feedback, the current-controlled oscillator changes frequency with change in the delay through the stages 20, 22, 24. Thus, the digital codes generate respective frequencies by oscillator delay.
  • the cascade of delay stages 20, 22 and 24 becomes a delay line with variable delay between an input to, and an output of, the delay line.
  • analog delay circuit of FIG. 1 permits it to be wholly integrated into an integrated circuit manufactured according to known techniques.
  • active semiconductor device technology including, but not limited to, IGFET, MOSFET, BIPOLAR, GaAsFET, or other, may be used without departing from the spirit of the invention. Therefore, an analog delay circuit of the invention may be fabricated, with one or more delay stages, in an integrated circuit such as the IC 50, together with other electronic circuits, such as 40 and 42 to provide a digital logic system.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

An analog delay circuit provide a current-dependent delay through two differential pairs of transistors operated in parallel, one with input resistors, the other without. Delay is varied through the delay stage by provision of complementary currents produced by a current DAC in response to digital code provided in a data bus. The complementary currents drive the differential pairs to various combinations of operations, which yields the desired variable delay.

Description

BACKGROUND OF THE INVENTION
The present invention relates to analog delay circuits, and particularly to analog circuits that present an adjustable, or variable, delay between input and output.
1. Field of the Invention
The introduction of a time delay Δ into a digital system has many useful applications. As pointed out by J. Millman, et al in Microelectronics, (McGraw-Hill, 1987) at page 328, where Δ is an integral multiple of a clock T, a shift register having n stages may be employed to delay an input pulse stream by a time (n-1) T=Δ.
It is useful that such delay be adjustable, particularly for purposes of intersignal synchronization in logic circuits. However, if the adjustment in Δ must respond to a continuously-variable voltage, or if it must be continuous itself, some or all, of the adjustment must be implemented in analog circuitry. In this regard, reference is given to U.S. Ser. No. 08/856,259, filed May 14, 1997, now U.S. Pat. No. 5,847,621, entitled "LC OSCILLATOR WITH DELAY TUNING", in which continuously-variable delay is used for tuning the frequency of a voltage-controlled oscillator (VCO). As is known, a VCO is a necessary component of a phase-locked loop. Therefore, implementation of variable delay in a form that can be accommodated in integrated circuit technology is highly desirable, especially in the mixed analog-digital VL,SI technology that is described, for example, by Y. Tsividis in Mixed Analog-Digital VLSI Devices And Technology, (McGraw-Hill, 1996). As Tsividis points out at page 3, mixed analog-digital circuits "help make possible the high performance of the digital systems and circuits themselves". Tsividis at p. 3.
Therefore a general need exists for the provision of mixed analog-digital circuits that will enhance the performance of digital systems. More specifically, a need exists for a voltage-controlled, variable analog delay circuit that can be built entirely in an integrated circuit (IC) for interfacing with digital circuits.
SUMMARY OF THE INVENTION
The invention is an analog delay circuit that yields a variable delay between an input signal and an output signal, wherein two differential pairs of transistors are connected in parallel, with a first of the differential pairs having a first signal path delay, and a second of the differential pairs having a second signal path delay. In each differential pair, the respective delay may be varied by varying a current provided to operate the differential pair. The differential pairs are connected to a current source, preferably embodied as a current digital-to-analog converter ("current DAC") that outputs a pair of complementary currents. A first current of the pair of complementary currents operates the first differential pair, while the second current operates the second differential pair. The current DAC is controlled by a digital code. As the digital code varies, the magnitudes of the complementary currents vary. As a consequence, the delays through the differential pairs vary. Since they operate in parallel, the differential pairs produce a composite variable delay that combines the individual variable delays. The invention therefore yields a current-controlled delay element that may be operated alone, or cascaded with one or more identical delay elements to provide either a variable-length delay line, a current-controlled oscillator with a variable frequency.
It is therefore an object of this invention to provide an analog delay circuit that may be implemented wholly in IC technology.
It is a further object of this invention to provide such an analog delay circuit having a delay that may be varied in response to a variable current.
A further object is to provide an analog delay circuit that may be combined with identical elements to provide a delay line whose total delay may be varied in response to a variable current.
Still another object is to provide a current-controlled oscillator with a frequency controlled by a digital code.
A thorough reading of the following Detailed Description in light of the accompanying drawings will confirm the achievement of these, and other, objectives.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is schematic diagram of an analog delay circuit according to this invention;
FIG. 2 is a representative plot of the complementary currents produced by a current DAC in response to an input digital code; and
FIG. 3 is block diagram of a ring oscillator constructed by cascading multiple delay stages, each of which embodies the analog delay circuit of FIG. 1.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to the drawings and figures in which identical reference numerals refer to identical elements, FIG. 1 is a schematic diagram of an analog delay circuit according to this invention. The analog delay circuit includes an analog delay element, or delay stage, 8 in combination with a current DAC 14. The delay stage 8 includes a pair of differential transistor pairs 10 and 12. The first differential transistor pair 10 includes emitter-coupled transistors Q1 and Q2, while the second differential pair 12 includes emitter-coupled transistors Q3 and Q4. The two differential pairs are connected to matched pull-up resistors R1 and R2. Each of the pull-up resistors is connected on one side to a collector of a respective transistor in each of the differential pairs 10 and 12, and on its other side to a collector voltage Vcc. In this regard, resistor R1 is connected to the collectors of transistors Q1 and Q3 and resistor R2 is connected to the collectors of transistors Q2 and Q4. Both resistors R1 and R2 are passive pull-up resistors that bias the transistors to whose collectors they are connected.
Each differential pair 10, 12 is essentially an analog amplifier that produces an output signal (OUT) in response to an input signal (IN).
Each of the differential pairs 10 and 12 is connected to an output of a current DAC 14. The current DAC 14 is conventional, producing a pair of complementary output currents (Iout/Iout) in response to a digital code input from a register 16. The current Iout sets the differential pair 10 to a level of operation, which may vary between off and full on. Similarly, the current Iout sets the differential pair 12 to a level of operation between off and full on. The relationship between the digital code and the pair of complementary output currents produced by the current DAC 14 is illustrated in FIG. 2. The digital code may be provided in a digital logic system by way of a data bus 17, or other appropriate means.
As will be appreciated, the differential pairs 10 and 12 are connected in parallel between Vcc and the current DAC 14.
The delay stage 8 receives the input signal (IN) comprising complementary inputs A/A, and, in response, produces the output (OUT) comprising complementary signals B/B. A delay time between the input and output signals is adjusted according to the composite level at which the two differential pairs 10 and 12 operate. Minimum delay (the fast case) occurs if Iout from the current DAC 14 is full scale, in which circumstance Q3 and Q4 are turned off, while Q1 and Q2 are turned completely on. In this case, the delay is essentially determined by the minimum parametric input values of the transistors Q1 and Q2. As the magnitude of Iout decreases, the response time, and therefore the delay through the differential pair 10 increases. The maximum delay (the slow case) occurs when the magnitude of Iout falls below the level required to keep Q1 and Q2 turned on; in this case, the magnitude of Iout turns Q3 and Q4 fully on. In the slow case, each of the matched resistors Rx and Ry forms a pole with the input capacitance of each of the transistors Q3 and Q4. This added pole in the signal path increases the delay through the differential pair 12 in comparison with that through the differential pair 10. As the magnitude of Iout decreases, the magnitude of Iout increases, and the composite delay through the delay stage 8 decreases. Consequently, by mixing a percentage of each of the fast and slow cases of biasing, with Iout and Iout at various combinations of magnitudes between their maximum and minimum values, in response to changes in the digital code applied to the DAC 14, a virtually continuous and monotonic time delay between the input and output signals through the delay stage 8 is realized.
FIG. 3 is a block diagram illustrating a current-controlled ring oscillator comprising delay stages 20, 22, and 24, each identical to the delay stage 8 illustrated in FIG. 1. Adjustment of delay through each of the stages 20, 22 and 24 is provided by a current DAC 30 that produces complementary DAC currents in the manner illustrated in FIGS. 1 and 2. The magnitudes of the complementary currents produced by the current DAC 30 are determined by a digital code registered at 32 and delivered by the data bus 33 in response to circuit operations of a digital logic system. With feedback, the current-controlled oscillator changes frequency with change in the delay through the stages 20, 22, 24. Thus, the digital codes generate respective frequencies by oscillator delay. Without feedback of the output of the delay stage 24 to the input of the delay stage 20, and with provision of an input signal to the input of the delay stage 20, the cascade of delay stages 20, 22 and 24 becomes a delay line with variable delay between an input to, and an output of, the delay line.
As those skilled in the art of IC technology fabrication will appreciate, the structure of the analog delay circuit of FIG. 1 permits it to be wholly integrated into an integrated circuit manufactured according to known techniques. The inventor contemplates that any appropriate active semiconductor device technology, including, but not limited to, IGFET, MOSFET, BIPOLAR, GaAsFET, or other, may be used without departing from the spirit of the invention. Therefore, an analog delay circuit of the invention may be fabricated, with one or more delay stages, in an integrated circuit such as the IC 50, together with other electronic circuits, such as 40 and 42 to provide a digital logic system.
While only certain preferred features of this invention have been shown by way of illustration, many changes and modifications will occur to those skilled in the art. Accordingly, it is to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims (11)

I claim:
1. A delay circuit, comprising:
a first differential pair of emitter-coupled transistors with a first adjustable delay;
at least a second differential pair of emitter-coupled transistors with a second adjustable delay;
the first and second differential pairs of emitter-coupled transistors being connected to a common input and a common output to provide a composite adjustable delay between the common input and common output that combines the first and second adjustable delays;
a register for containing a digital code;
a current digital-to-analog converter (DAC) connected to the register for providing a pair of complementary currents in response to the digital code, the current DAC being connected to provide a first current of the pair of complementary currents to the first differential pair and to provide a second current of the pair of complementary currents to the second differential pair; and,
wherein the first and second differential pairs each include first and second emitter-coupled transistors, the delay circuit further including a first resistor connected to the base of a first transistor of the second differential pair and a second resistor connected to the base of a second transistor of the second differential pair.
2. The delay circuit of claim 1, further including means connected to the register for providing the digital code.
3. The delay circuit of claim 2, wherein the means includes a data bus.
4. An integrated circuit with one or more electronic circuits, in which at least one of the electronic circuits includes an analog delay circuit having:
a first differential pair of emitter-coupled transistors with a first adjustable delay;
at least a second differential pair of emitter-coupled transistors with a second adjustable delay;
the first and second differential pairs of emitter-coupled transistors being connected to a common input and a common output to provide a composite adjustable delay between the common input and common output that combines the first and second adjustable delays;
a register for containing a digital code;
a current digital-to-analog converter (DAC) connected to the register for providing a pair of complementary currents in response to the digital code, the current DAC being connected to provide a first current of the pair of complementary currents to the first differential pair and to provide a second current of the pair of complementary currents to the second differential pair; and,
wherein the first and second differential pairs each include first and second emitter-coupled transistors, the delay circuit further including a first resistor connected to the base of a first transistor of the second differential pair and a second resistor connected to the base of a second transistor of the second differential pair.
5. The integrated circuit of claim 4, wherein the analog delay circuit further includes means connected to the register for providing the digital code.
6. The integrated circuit of claim 5, wherein the means includes a data bus.
7. A delay circuit comprising:
a plurality of cascaded delay stages, each delay stage including a common input and a common output, and:
a first differential pair of emitter-coupled transistors with a first adjustable delay;
at least a second differential pair of emitter-coupled transistors with a second adjustable delay; and
the first and second differential pairs of emitter-coupled transistors being connected to the common input and the common output to provide a composite adjustable delay between the common input and common output that combines the first and second adjustable delays;
a register for containing a digital code;
a current digital-to-analog converter (DAC) connected to the register for providing a pair of complementary currents in response to the digital code, the current DAC being connected to provide a first current of the pair of complementary currents to the first differential pair of each delay stage and to provide a second current of the pair of complementary currents to the second differential pair of each delay stage; and,
wherein, for said each delay stage, the first and second differential pairs each include first and second emitter-coupled transistors, said each delay stage further including a first resistor connected to the base of a first transistor of the second differential pair and a second resistor connected to the base of a second transistor of the second differential pair.
8. The delay circuit of claim 7, further including means connected to the register for providing the digital code.
9. The delay circuit of claim 8, wherein the means includes a data bus.
10. An integrated circuit with one or more electronic circuits, at least one electronic circuit including the delay circuit of claim 7.
11. The integrated circuit of claim 10, wherein the delay circuit includes semiconductor devices selected from the group including IFET, MOSFET, BIPOLAR, and GaSaFET devices.
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Cited By (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6177822B1 (en) * 1997-12-25 2001-01-23 Nec Corporation Variable phase shifting circuit manufactured in simple integrated circuit
US6222423B1 (en) * 1999-02-03 2001-04-24 Micro Linear Corporation Voltage controlled ring oscillator delay
WO2001071919A2 (en) * 2000-03-17 2001-09-27 Motorola, Inc. Bias modulated oscillator and method
US6329859B1 (en) * 2000-03-23 2001-12-11 Bitblitz Communications, Inc. N-way circular phase interpolator for generating a signal having arbitrary phase
US6340899B1 (en) 2000-02-24 2002-01-22 Broadcom Corporation Current-controlled CMOS circuits with inductive broadbanding
US6424194B1 (en) 1999-06-28 2002-07-23 Broadcom Corporation Current-controlled CMOS logic family
US20040056698A1 (en) * 2002-09-25 2004-03-25 Ken Elliott Time delay apparatus and method of using same
US20040100147A1 (en) * 2002-11-26 2004-05-27 Realtek Semiconductor Corp. Apparatus for inhibiting ring back effect of circuit and method thereof
US20040229591A1 (en) * 2003-05-14 2004-11-18 Semiconductor Components Industries, Llc. High speed receiver with wide input voltage range
US6897697B2 (en) 1999-06-28 2005-05-24 Broadcom Corporation Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
US6911855B2 (en) 1999-06-28 2005-06-28 Broadcom Corporation Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
US7362174B2 (en) 2005-07-29 2008-04-22 Broadcom Corporation Current-controlled CMOS (C3MOS) wideband input data amplifier for reduced differential and common-mode reflection
US20090025023A1 (en) * 2007-06-06 2009-01-22 Neurofocus Inc. Multi-market program and commercial response monitoring system using neuro-response measurements
US20090024049A1 (en) * 2007-03-29 2009-01-22 Neurofocus, Inc. Cross-modality synthesis of central nervous system, autonomic nervous system, and effector data
US7598811B2 (en) 2005-07-29 2009-10-06 Broadcom Corporation Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading
US7598788B2 (en) 2005-09-06 2009-10-06 Broadcom Corporation Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth
US7849208B2 (en) 2002-08-30 2010-12-07 Broadcom Corporation System and method for TCP offload
US7912064B2 (en) 2002-08-30 2011-03-22 Broadcom Corporation System and method for handling out-of-order frames
US20110078762A1 (en) * 2009-09-29 2011-03-31 Ebay, Inc. Mobile or user device authentication and tracking
US7934021B2 (en) 2002-08-29 2011-04-26 Broadcom Corporation System and method for network interfacing
US8116203B2 (en) 2001-07-23 2012-02-14 Broadcom Corporation Multiple virtual channels for use in network devices
US8135016B2 (en) 2002-03-08 2012-03-13 Broadcom Corporation System and method for identifying upper layer protocol message boundaries
US8180928B2 (en) 2002-08-30 2012-05-15 Broadcom Corporation Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney
US8335715B2 (en) 2009-11-19 2012-12-18 The Nielsen Company (Us), Llc. Advertisement exchange using neuro-response data
US8335716B2 (en) 2009-11-19 2012-12-18 The Nielsen Company (Us), Llc. Multimedia advertisement exchange
US8386312B2 (en) 2007-05-01 2013-02-26 The Nielsen Company (Us), Llc Neuro-informatics repository system
US8386313B2 (en) 2007-08-28 2013-02-26 The Nielsen Company (Us), Llc Stimulus placement system using subject neuro-response measurements
US8392255B2 (en) 2007-08-29 2013-03-05 The Nielsen Company (Us), Llc Content based selection and meta tagging of advertisement breaks
US8392253B2 (en) 2007-05-16 2013-03-05 The Nielsen Company (Us), Llc Neuro-physiology and neuro-behavioral based stimulus targeting system
US8392250B2 (en) 2010-08-09 2013-03-05 The Nielsen Company (Us), Llc Neuro-response evaluated stimulus in virtual reality environments
US8392254B2 (en) 2007-08-28 2013-03-05 The Nielsen Company (Us), Llc Consumer experience assessment system
US8392251B2 (en) 2010-08-09 2013-03-05 The Nielsen Company (Us), Llc Location aware presentation of stimulus material
US8396744B2 (en) 2010-08-25 2013-03-12 The Nielsen Company (Us), Llc Effective virtual reality environments for presentation of marketing materials
US8402142B2 (en) 2002-08-30 2013-03-19 Broadcom Corporation System and method for TCP/IP offload independent of bandwidth delay product
US8464288B2 (en) 2009-01-21 2013-06-11 The Nielsen Company (Us), Llc Methods and apparatus for providing personalized media in video
US8494905B2 (en) 2007-06-06 2013-07-23 The Nielsen Company (Us), Llc Audience response analysis using simultaneous electroencephalography (EEG) and functional magnetic resonance imaging (fMRI)
US8494610B2 (en) 2007-09-20 2013-07-23 The Nielsen Company (Us), Llc Analysis of marketing and entertainment effectiveness using magnetoencephalography
US8533042B2 (en) 2007-07-30 2013-09-10 The Nielsen Company (Us), Llc Neuro-response stimulus and stimulus attribute resonance estimator
US8635105B2 (en) 2007-08-28 2014-01-21 The Nielsen Company (Us), Llc Consumer experience portrayal effectiveness assessment system
US8655437B2 (en) 2009-08-21 2014-02-18 The Nielsen Company (Us), Llc Analysis of the mirror neuron system for evaluation of stimulus
US8655428B2 (en) 2010-05-12 2014-02-18 The Nielsen Company (Us), Llc Neuro-response data synchronization
US8750320B2 (en) 1997-01-23 2014-06-10 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US8762202B2 (en) 2009-10-29 2014-06-24 The Nielson Company (Us), Llc Intracluster content management using neuro-response priming data
US8798091B2 (en) 1998-11-19 2014-08-05 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US20140265578A1 (en) * 2013-03-14 2014-09-18 Analog Devices, Inc. Fine timing adjustment method
US8977110B2 (en) 2009-01-21 2015-03-10 The Nielsen Company (Us), Llc Methods and apparatus for providing video with embedded media
US8989835B2 (en) 2012-08-17 2015-03-24 The Nielsen Company (Us), Llc Systems and methods to gather and analyze electroencephalographic data
US9320450B2 (en) 2013-03-14 2016-04-26 The Nielsen Company (Us), Llc Methods and apparatus to gather and analyze electroencephalographic data
US9357240B2 (en) 2009-01-21 2016-05-31 The Nielsen Company (Us), Llc Methods and apparatus for providing alternate media for video decoders
US9454646B2 (en) 2010-04-19 2016-09-27 The Nielsen Company (Us), Llc Short imagery task (SIT) research method
US9560984B2 (en) 2009-10-29 2017-02-07 The Nielsen Company (Us), Llc Analysis of controlled and automatic attention for introduction of stimulus material
US9569986B2 (en) 2012-02-27 2017-02-14 The Nielsen Company (Us), Llc System and method for gathering and analyzing biometric user feedback for use in social media and advertising applications
US20170047917A1 (en) * 2014-04-16 2017-02-16 Washington State University Signal delay cells
US9622703B2 (en) 2014-04-03 2017-04-18 The Nielsen Company (Us), Llc Methods and apparatus to gather and analyze electroencephalographic data
US9886981B2 (en) 2007-05-01 2018-02-06 The Nielsen Company (Us), Llc Neuro-feedback based stimulus compression device
US9936250B2 (en) 2015-05-19 2018-04-03 The Nielsen Company (Us), Llc Methods and apparatus to adjust content presented to an individual
US10963895B2 (en) 2007-09-20 2021-03-30 Nielsen Consumer Llc Personalized content delivery using neuro-response priming data
US10987015B2 (en) 2009-08-24 2021-04-27 Nielsen Consumer Llc Dry electrodes for electroencephalography
US11481788B2 (en) 2009-10-29 2022-10-25 Nielsen Consumer Llc Generating ratings predictions using neuro-response data
US11704681B2 (en) 2009-03-24 2023-07-18 Nielsen Consumer Llc Neurological profiles for market matching and stimulus presentation

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4052679A (en) * 1975-04-14 1977-10-04 Sanyo Electric Co., Ltd. Phase shifting circuit
US4795923A (en) * 1987-11-25 1989-01-03 Tektronix, Inc. Adjustable delay circuit
US4797586A (en) * 1987-11-25 1989-01-10 Tektronix, Inc. Controllable delay circuit
US4866314A (en) * 1986-07-18 1989-09-12 Tektronix, Inc. Programmable high-speed digital delay circuit
US5066877A (en) * 1989-01-19 1991-11-19 Fujitsu Limited Data delay circuit and clock extraction circuit using the same
US5086500A (en) * 1987-08-07 1992-02-04 Tektronix, Inc. Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits
US5087842A (en) * 1988-01-06 1992-02-11 Digital Equipment Corporation Delay circuit having one of a plurality of delay lines which may be selected to provide an operation of a ring oscillator
US5138204A (en) * 1990-09-28 1992-08-11 Makoto Imamura Adjustable delay utilizing a mirror capacitance discharging a constant current in the saturation and linear regions of a mirror amplifier
US5218363A (en) * 1982-04-12 1993-06-08 Lecroy Corporation High-speed switching tree with input sampling pulses of constant frequency and means for varying the effective sampling rate
US5327031A (en) * 1992-03-24 1994-07-05 Bull S.A. Variable-delay circuit
US5463343A (en) * 1990-12-27 1995-10-31 Bull, S.A. Adjustable delay circuit of the current intensity having delay as a hyperbolic function
US5528186A (en) * 1994-03-22 1996-06-18 Yokogawa Electric Corporation Timing generator using digital signals to obtain accurate delay time and high resolution

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4052679A (en) * 1975-04-14 1977-10-04 Sanyo Electric Co., Ltd. Phase shifting circuit
US5218363A (en) * 1982-04-12 1993-06-08 Lecroy Corporation High-speed switching tree with input sampling pulses of constant frequency and means for varying the effective sampling rate
US4866314A (en) * 1986-07-18 1989-09-12 Tektronix, Inc. Programmable high-speed digital delay circuit
US5086500A (en) * 1987-08-07 1992-02-04 Tektronix, Inc. Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits
US4795923A (en) * 1987-11-25 1989-01-03 Tektronix, Inc. Adjustable delay circuit
US4797586A (en) * 1987-11-25 1989-01-10 Tektronix, Inc. Controllable delay circuit
US5087842A (en) * 1988-01-06 1992-02-11 Digital Equipment Corporation Delay circuit having one of a plurality of delay lines which may be selected to provide an operation of a ring oscillator
US5066877A (en) * 1989-01-19 1991-11-19 Fujitsu Limited Data delay circuit and clock extraction circuit using the same
US5138204A (en) * 1990-09-28 1992-08-11 Makoto Imamura Adjustable delay utilizing a mirror capacitance discharging a constant current in the saturation and linear regions of a mirror amplifier
US5463343A (en) * 1990-12-27 1995-10-31 Bull, S.A. Adjustable delay circuit of the current intensity having delay as a hyperbolic function
US5327031A (en) * 1992-03-24 1994-07-05 Bull S.A. Variable-delay circuit
US5528186A (en) * 1994-03-22 1996-06-18 Yokogawa Electric Corporation Timing generator using digital signals to obtain accurate delay time and high resolution

Cited By (127)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8750320B2 (en) 1997-01-23 2014-06-10 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US8767756B2 (en) 1997-01-23 2014-07-01 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US8774199B2 (en) 1997-01-23 2014-07-08 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US6177822B1 (en) * 1997-12-25 2001-01-23 Nec Corporation Variable phase shifting circuit manufactured in simple integrated circuit
US8798091B2 (en) 1998-11-19 2014-08-05 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US6222423B1 (en) * 1999-02-03 2001-04-24 Micro Linear Corporation Voltage controlled ring oscillator delay
US8823435B2 (en) 1999-06-28 2014-09-02 Broadcom Corporation Current-controlled CMOS logic family
US6937080B2 (en) 1999-06-28 2005-08-30 Broadcom Corporation Current-controlled CMOS logic family
US10396763B2 (en) 1999-06-28 2019-08-27 Avago Technologies International Sales Pte. Limited Current-controlled CMOS logic family
US9831853B2 (en) 1999-06-28 2017-11-28 Avago Technologies General Ip (Singapore) Pte. Ltd. Current-controlled CMOS logic family
US9112487B2 (en) 1999-06-28 2015-08-18 Broadcom Corporation Current-controlled CMOS logic family
US6897697B2 (en) 1999-06-28 2005-05-24 Broadcom Corporation Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
US6900670B2 (en) 1999-06-28 2005-05-31 Broadcom Corporation Current-controlled CMOS logic family
US6424194B1 (en) 1999-06-28 2002-07-23 Broadcom Corporation Current-controlled CMOS logic family
US6911855B2 (en) 1999-06-28 2005-06-28 Broadcom Corporation Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
US7724057B2 (en) 1999-06-28 2010-05-25 Broadcom Corporation Current-controlled CMOS logic family
US8299834B2 (en) 1999-06-28 2012-10-30 Broadcom Corporation Current-controlled CMOS logic family
US7919985B2 (en) 2000-02-24 2011-04-05 Broadcom Corporation Current-controlled CMOS circuits with inductive broadbanding
US6525571B2 (en) 2000-02-24 2003-02-25 Broadcom Corporation Current-controlled CMOS circuits with inductive broadbanding
US6909309B2 (en) 2000-02-24 2005-06-21 Broadcom Corporation Current-controlled CMOS circuits with inductive broadbanding
US6340899B1 (en) 2000-02-24 2002-01-22 Broadcom Corporation Current-controlled CMOS circuits with inductive broadbanding
WO2001071919A3 (en) * 2000-03-17 2003-02-06 Motorola Inc Bias modulated oscillator and method
WO2001071919A2 (en) * 2000-03-17 2001-09-27 Motorola, Inc. Bias modulated oscillator and method
US6329859B1 (en) * 2000-03-23 2001-12-11 Bitblitz Communications, Inc. N-way circular phase interpolator for generating a signal having arbitrary phase
US9036643B2 (en) 2001-07-23 2015-05-19 Broadcom Corporation Multiple logical channels for use in network devices
US8493857B2 (en) 2001-07-23 2013-07-23 Broadcom Corporation Multiple logical channels for use in network devices
US8116203B2 (en) 2001-07-23 2012-02-14 Broadcom Corporation Multiple virtual channels for use in network devices
US8451863B2 (en) 2002-03-08 2013-05-28 Broadcom Corporation System and method for identifying upper layer protocol message boundaries
US8345689B2 (en) 2002-03-08 2013-01-01 Broadcom Corporation System and method for identifying upper layer protocol message boundaries
US8958440B2 (en) 2002-03-08 2015-02-17 Broadcom Corporation System and method for identifying upper layer protocol message boundaries
US8135016B2 (en) 2002-03-08 2012-03-13 Broadcom Corporation System and method for identifying upper layer protocol message boundaries
US7934021B2 (en) 2002-08-29 2011-04-26 Broadcom Corporation System and method for network interfacing
US8677010B2 (en) 2002-08-30 2014-03-18 Broadcom Corporation System and method for TCP offload
US8180928B2 (en) 2002-08-30 2012-05-15 Broadcom Corporation Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney
US7912064B2 (en) 2002-08-30 2011-03-22 Broadcom Corporation System and method for handling out-of-order frames
US8549152B2 (en) 2002-08-30 2013-10-01 Broadcom Corporation System and method for TCP/IP offload independent of bandwidth delay product
US7849208B2 (en) 2002-08-30 2010-12-07 Broadcom Corporation System and method for TCP offload
US8402142B2 (en) 2002-08-30 2013-03-19 Broadcom Corporation System and method for TCP/IP offload independent of bandwidth delay product
US7929540B2 (en) 2002-08-30 2011-04-19 Broadcom Corporation System and method for handling out-of-order frames
US20040056698A1 (en) * 2002-09-25 2004-03-25 Ken Elliott Time delay apparatus and method of using same
US7446584B2 (en) * 2002-09-25 2008-11-04 Hrl Laboratories, Llc Time delay apparatus and method of using same
US20040100147A1 (en) * 2002-11-26 2004-05-27 Realtek Semiconductor Corp. Apparatus for inhibiting ring back effect of circuit and method thereof
US7132857B2 (en) * 2003-05-14 2006-11-07 Semiconductor Components Industries, L.L.C. High speed receiver with wide input voltage range
US20040229591A1 (en) * 2003-05-14 2004-11-18 Semiconductor Components Industries, Llc. High speed receiver with wide input voltage range
US20100013557A1 (en) * 2005-07-29 2010-01-21 Broadcom Corporation Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading
US7598811B2 (en) 2005-07-29 2009-10-06 Broadcom Corporation Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading
US7902924B2 (en) 2005-07-29 2011-03-08 Broadcom Corporation Current-controlled CMOS (C3MOS) fully differential integrated wideband amplifier/equalizer with adjustable gain and frequency response without additional power or loading
US7362174B2 (en) 2005-07-29 2008-04-22 Broadcom Corporation Current-controlled CMOS (C3MOS) wideband input data amplifier for reduced differential and common-mode reflection
US7598788B2 (en) 2005-09-06 2009-10-06 Broadcom Corporation Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth
US20100019817A1 (en) * 2005-09-06 2010-01-28 Broadcom Corporation Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth
US20090024049A1 (en) * 2007-03-29 2009-01-22 Neurofocus, Inc. Cross-modality synthesis of central nervous system, autonomic nervous system, and effector data
US10679241B2 (en) 2007-03-29 2020-06-09 The Nielsen Company (Us), Llc Analysis of marketing and entertainment effectiveness using central nervous system, autonomic nervous system, and effector data
US8473345B2 (en) 2007-03-29 2013-06-25 The Nielsen Company (Us), Llc Protocol generator and presenter device for analysis of marketing and entertainment effectiveness
US8484081B2 (en) 2007-03-29 2013-07-09 The Nielsen Company (Us), Llc Analysis of marketing and entertainment effectiveness using central nervous system, autonomic nervous system, and effector data
US11250465B2 (en) 2007-03-29 2022-02-15 Nielsen Consumer Llc Analysis of marketing and entertainment effectiveness using central nervous system, autonomic nervous sytem, and effector data
US11790393B2 (en) 2007-03-29 2023-10-17 Nielsen Consumer Llc Analysis of marketing and entertainment effectiveness using central nervous system, autonomic nervous system, and effector data
US8386312B2 (en) 2007-05-01 2013-02-26 The Nielsen Company (Us), Llc Neuro-informatics repository system
US9886981B2 (en) 2007-05-01 2018-02-06 The Nielsen Company (Us), Llc Neuro-feedback based stimulus compression device
US10580031B2 (en) 2007-05-16 2020-03-03 The Nielsen Company (Us), Llc Neuro-physiology and neuro-behavioral based stimulus targeting system
US8392253B2 (en) 2007-05-16 2013-03-05 The Nielsen Company (Us), Llc Neuro-physiology and neuro-behavioral based stimulus targeting system
US11049134B2 (en) 2007-05-16 2021-06-29 Nielsen Consumer Llc Neuro-physiology and neuro-behavioral based stimulus targeting system
US8494905B2 (en) 2007-06-06 2013-07-23 The Nielsen Company (Us), Llc Audience response analysis using simultaneous electroencephalography (EEG) and functional magnetic resonance imaging (fMRI)
US20090025023A1 (en) * 2007-06-06 2009-01-22 Neurofocus Inc. Multi-market program and commercial response monitoring system using neuro-response measurements
US10733625B2 (en) 2007-07-30 2020-08-04 The Nielsen Company (Us), Llc Neuro-response stimulus and stimulus attribute resonance estimator
US11244345B2 (en) 2007-07-30 2022-02-08 Nielsen Consumer Llc Neuro-response stimulus and stimulus attribute resonance estimator
US11763340B2 (en) 2007-07-30 2023-09-19 Nielsen Consumer Llc Neuro-response stimulus and stimulus attribute resonance estimator
US8533042B2 (en) 2007-07-30 2013-09-10 The Nielsen Company (Us), Llc Neuro-response stimulus and stimulus attribute resonance estimator
US11488198B2 (en) 2007-08-28 2022-11-01 Nielsen Consumer Llc Stimulus placement system using subject neuro-response measurements
US10127572B2 (en) 2007-08-28 2018-11-13 The Nielsen Company, (US), LLC Stimulus placement system using subject neuro-response measurements
US8635105B2 (en) 2007-08-28 2014-01-21 The Nielsen Company (Us), Llc Consumer experience portrayal effectiveness assessment system
US8392254B2 (en) 2007-08-28 2013-03-05 The Nielsen Company (Us), Llc Consumer experience assessment system
US10937051B2 (en) 2007-08-28 2021-03-02 The Nielsen Company (Us), Llc Stimulus placement system using subject neuro-response measurements
US8386313B2 (en) 2007-08-28 2013-02-26 The Nielsen Company (Us), Llc Stimulus placement system using subject neuro-response measurements
US8392255B2 (en) 2007-08-29 2013-03-05 The Nielsen Company (Us), Llc Content based selection and meta tagging of advertisement breaks
US11610223B2 (en) 2007-08-29 2023-03-21 Nielsen Consumer Llc Content based selection and meta tagging of advertisement breaks
US10140628B2 (en) 2007-08-29 2018-11-27 The Nielsen Company, (US), LLC Content based selection and meta tagging of advertisement breaks
US11023920B2 (en) 2007-08-29 2021-06-01 Nielsen Consumer Llc Content based selection and meta tagging of advertisement breaks
US8494610B2 (en) 2007-09-20 2013-07-23 The Nielsen Company (Us), Llc Analysis of marketing and entertainment effectiveness using magnetoencephalography
US10963895B2 (en) 2007-09-20 2021-03-30 Nielsen Consumer Llc Personalized content delivery using neuro-response priming data
US8955010B2 (en) 2009-01-21 2015-02-10 The Nielsen Company (Us), Llc Methods and apparatus for providing personalized media in video
US9357240B2 (en) 2009-01-21 2016-05-31 The Nielsen Company (Us), Llc Methods and apparatus for providing alternate media for video decoders
US8464288B2 (en) 2009-01-21 2013-06-11 The Nielsen Company (Us), Llc Methods and apparatus for providing personalized media in video
US8977110B2 (en) 2009-01-21 2015-03-10 The Nielsen Company (Us), Llc Methods and apparatus for providing video with embedded media
US9826284B2 (en) 2009-01-21 2017-11-21 The Nielsen Company (Us), Llc Methods and apparatus for providing alternate media for video decoders
US11704681B2 (en) 2009-03-24 2023-07-18 Nielsen Consumer Llc Neurological profiles for market matching and stimulus presentation
US8655437B2 (en) 2009-08-21 2014-02-18 The Nielsen Company (Us), Llc Analysis of the mirror neuron system for evaluation of stimulus
US10987015B2 (en) 2009-08-24 2021-04-27 Nielsen Consumer Llc Dry electrodes for electroencephalography
US20110078762A1 (en) * 2009-09-29 2011-03-31 Ebay, Inc. Mobile or user device authentication and tracking
US10068248B2 (en) 2009-10-29 2018-09-04 The Nielsen Company (Us), Llc Analysis of controlled and automatic attention for introduction of stimulus material
US9560984B2 (en) 2009-10-29 2017-02-07 The Nielsen Company (Us), Llc Analysis of controlled and automatic attention for introduction of stimulus material
US11669858B2 (en) 2009-10-29 2023-06-06 Nielsen Consumer Llc Analysis of controlled and automatic attention for introduction of stimulus material
US11481788B2 (en) 2009-10-29 2022-10-25 Nielsen Consumer Llc Generating ratings predictions using neuro-response data
US11170400B2 (en) 2009-10-29 2021-11-09 Nielsen Consumer Llc Analysis of controlled and automatic attention for introduction of stimulus material
US10269036B2 (en) 2009-10-29 2019-04-23 The Nielsen Company (Us), Llc Analysis of controlled and automatic attention for introduction of stimulus material
US8762202B2 (en) 2009-10-29 2014-06-24 The Nielson Company (Us), Llc Intracluster content management using neuro-response priming data
US8335716B2 (en) 2009-11-19 2012-12-18 The Nielsen Company (Us), Llc. Multimedia advertisement exchange
US8335715B2 (en) 2009-11-19 2012-12-18 The Nielsen Company (Us), Llc. Advertisement exchange using neuro-response data
US10248195B2 (en) 2010-04-19 2019-04-02 The Nielsen Company (Us), Llc. Short imagery task (SIT) research method
US11200964B2 (en) 2010-04-19 2021-12-14 Nielsen Consumer Llc Short imagery task (SIT) research method
US9454646B2 (en) 2010-04-19 2016-09-27 The Nielsen Company (Us), Llc Short imagery task (SIT) research method
US9336535B2 (en) 2010-05-12 2016-05-10 The Nielsen Company (Us), Llc Neuro-response data synchronization
US8655428B2 (en) 2010-05-12 2014-02-18 The Nielsen Company (Us), Llc Neuro-response data synchronization
US8392251B2 (en) 2010-08-09 2013-03-05 The Nielsen Company (Us), Llc Location aware presentation of stimulus material
US8392250B2 (en) 2010-08-09 2013-03-05 The Nielsen Company (Us), Llc Neuro-response evaluated stimulus in virtual reality environments
US8548852B2 (en) 2010-08-25 2013-10-01 The Nielsen Company (Us), Llc Effective virtual reality environments for presentation of marketing materials
US8396744B2 (en) 2010-08-25 2013-03-12 The Nielsen Company (Us), Llc Effective virtual reality environments for presentation of marketing materials
US9569986B2 (en) 2012-02-27 2017-02-14 The Nielsen Company (Us), Llc System and method for gathering and analyzing biometric user feedback for use in social media and advertising applications
US10881348B2 (en) 2012-02-27 2021-01-05 The Nielsen Company (Us), Llc System and method for gathering and analyzing biometric user feedback for use in social media and advertising applications
US10842403B2 (en) 2012-08-17 2020-11-24 The Nielsen Company (Us), Llc Systems and methods to gather and analyze electroencephalographic data
US10779745B2 (en) 2012-08-17 2020-09-22 The Nielsen Company (Us), Llc Systems and methods to gather and analyze electroencephalographic data
US9060671B2 (en) 2012-08-17 2015-06-23 The Nielsen Company (Us), Llc Systems and methods to gather and analyze electroencephalographic data
US8989835B2 (en) 2012-08-17 2015-03-24 The Nielsen Company (Us), Llc Systems and methods to gather and analyze electroencephalographic data
US11980469B2 (en) 2012-08-17 2024-05-14 Nielsen Company Systems and methods to gather and analyze electroencephalographic data
US9215978B2 (en) 2012-08-17 2015-12-22 The Nielsen Company (Us), Llc Systems and methods to gather and analyze electroencephalographic data
US9907482B2 (en) 2012-08-17 2018-03-06 The Nielsen Company (Us), Llc Systems and methods to gather and analyze electroencephalographic data
US9887552B2 (en) * 2013-03-14 2018-02-06 Analog Devices, Inc. Fine timing adjustment method
US11076807B2 (en) 2013-03-14 2021-08-03 Nielsen Consumer Llc Methods and apparatus to gather and analyze electroencephalographic data
US9668694B2 (en) 2013-03-14 2017-06-06 The Nielsen Company (Us), Llc Methods and apparatus to gather and analyze electroencephalographic data
US9320450B2 (en) 2013-03-14 2016-04-26 The Nielsen Company (Us), Llc Methods and apparatus to gather and analyze electroencephalographic data
US20140265578A1 (en) * 2013-03-14 2014-09-18 Analog Devices, Inc. Fine timing adjustment method
US11141108B2 (en) 2014-04-03 2021-10-12 Nielsen Consumer Llc Methods and apparatus to gather and analyze electroencephalographic data
US9622703B2 (en) 2014-04-03 2017-04-18 The Nielsen Company (Us), Llc Methods and apparatus to gather and analyze electroencephalographic data
US9622702B2 (en) 2014-04-03 2017-04-18 The Nielsen Company (Us), Llc Methods and apparatus to gather and analyze electroencephalographic data
US20170047917A1 (en) * 2014-04-16 2017-02-16 Washington State University Signal delay cells
US11290779B2 (en) 2015-05-19 2022-03-29 Nielsen Consumer Llc Methods and apparatus to adjust content presented to an individual
US10771844B2 (en) 2015-05-19 2020-09-08 The Nielsen Company (Us), Llc Methods and apparatus to adjust content presented to an individual
US9936250B2 (en) 2015-05-19 2018-04-03 The Nielsen Company (Us), Llc Methods and apparatus to adjust content presented to an individual

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